Information

DMA Controller (DMAC)
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 12-19
Table 12-18 describes the TCD word 2 fields.
Figure 12-18 shows the TCD word 3 field.
Offset DMA_Offset = 0x1000 + 0x08 Access: Read/Write
31 30 29 10 9 0
R
smloe dmloe nbytes[29:10] or mloff [19:0] nbytes[9:0]
W
Reset All zeros
Figure 12-17. TCD Word 2 (TCD.{smloe, dmloe, nbytes}) Field
Table 12-18. TCD Word 2 (TCD.{smloe, dmloe, nbytes}) Description
Bits Name Description
31 smloe Source minor loop offset enable. This flag selects whether the minor loop offset is applied to the
source address upon minor loop completion.
0 The minor loop offset is not applied to the saddr.
1 The minor loop offset is applied to the saddr.
30 dmloe Destination minor loop offset enable. This flag selects whether the minor loop offset is applied to the
destination address upon minor loop completion.
0 The minor loop offset is not applied to the daddr.
1 The minor loop offset is applied to the daddr.
nbytes
[29:10] or
mloff[19:0]
nbytes
[29:10] or
mloff[19:0]
Inner minor byte transfer count or minor loop offset. If both smloe and dmloe are cleared, this field is
part of the byte transfer count. If either smloe or dmloe are set, this field represents a sign-extended
offset applied to the source or destination address to form the next-state value after the minor loop is
completed.
nbytes[9:0] nbytes[9:0] Inner minor byte transfer count. Number of bytes to be transferred in each service request of the
channel. As a channel is activated, the contents of the appropriate TCD is loaded into the
dma_engine, and the appropriate reads and writes performed until the complete byte transfer count
has been transferred. This is an indivisible operation and cannot be stalled or halted. Once the minor
count is exhausted, the current values of the saddr and daddr are written back into the local memory,
the major iteration count is decremented and restored to the local memory. If the major iteration count
is completed, additional processing is performed. This field is extended to 30 bits when both smloe
and dmloe are cleared (disabled).
Offset DMA_Offset = 0x1000 + (32 x n) + 0x0C Access: Read/Write
31 16
R
slast[31–16]
W
Reset All zeros
15 0
R
slast[15–0]
W
Reset All zeros
Figure 12-18. TCD Word 3 (TCDn.slast) Field