Information

DMA Controller (DMAC)
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
12-18 Freescale Semiconductor
Figure 12-16 shows the TCD word 1 field.
Table 12-17 describes the TCD word 1 fields.
When minor loop mapping (DMACR[EMLM] = 1) is enabled, TCD word2, shown in Figure 12-17, is
redefined as four fields: a source minor loop offset enable, a destination minor loop offset enable, a minor
loop offset field, and a nbytes field.
Offset DMA_Offset = 0x1000 + (32  n) + 0x04 Access: Read/Write
31 27 26 24 23 19 18 16
R
smod[4–0] ssize[2–0] dmod[4–0] dsize[2–0]
W
Reset All zeros
15 0
R
soff[15–0]
W
Reset All zeros
Figure 12-16. TCD Word 1 (TCDn.{soff, smod, ssize, dmod, dsize}) Fields
Table 12-17. TCD Word 1 (TCD.{smod, ssize, dmod, dsize, soff}) Field Descriptions
Bits Name Description
31–27 smod Source address modulo.
0 Source address modulo feature is disabled.
Other The value defines a specific address bit which is selected to be either the value after saddr + soff
calculation is performed or the original register value. This feature provides the ability to easily
implement a circular data queue. For data queues requiring power-of-2 ‘size’ bytes, the queue should
be based at a 0-modulo-size address and the smod field set to the appropriate value to freeze the
upper address bits. The bit select is defined as ((1 << smod[4:0]) – 1) where a resulting 1 in a bit
location selects the next state address for the corresponding address bit location and a 0 selects the
original register value for the corresponding address bit location. For this application, the soff is
typically set to the transfer size to implement post-increment addressing with the smod function
constraining the addresses to a 0-modulo-size range.
26–24 ssize Source data transfer size.
000 8-bit
001 16-bit
010 32-bit
011 64-bit
100 16-byte
100 Reserved
101 32-byte
110 Reserved
111 Reserved
23–19 dmod Destination address modulo. See the smod definition.
18–16 dsize Destination data transfer size. See the ssize definition.
15–0 soff Source address signed offset. Sign-extended offset applied to the current source address to form the
next-state value as each source read is completed.