Information

DMA Controller (DMAC)
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 12-17
1, ..., channel [n – 1]. The definitions of the TCD are presented as eight 32-bit values. Table 12-15 is a
32-bit view of the basic TCD structure.
Figure 12-15 shows the TCD word 0 field.
Table 12-16 describes the TCD word 0 fields.
Table 12-15. TCD 32-Bit Memory Structure
DMA Offset TCD Field
0x1000 + (32 x n) + 0x000 Source Address (saddr)
0x1000 + (32 x n) + 0x004 Transfer Attributes
(smod, ssize, dmod, dsize)
Signed Source Address Offset (soff)
0x1000 + (32 x n) + 0x008 Inner Minor Byte
Count (nbytes)
0x1000 + (32 x n) + 0x0C Last Source Address Adjustment (slast)
0x1000 + (32 x n) + 0x010 Destination Address (daddr)
0x1000 + (32 x n) + 0x014 Current Major Iteration Count (citer) Signed Destination Address Offset (doff)
0x1000 + (32 x n) + 0x018 Last Destination Address Adjustment/Scatter Gather Address (dlast_sga)
0x1000 + (32 x n) + 0x01C Beginning Major Iteration Count (biter) Channel Control/Status
(bwc, major.linkch, done, active, major.e_link,
e_sg, d_req, int_half, int_maj, start)
Offset DMA_Offset = 0x1000 + (32 x n) + 0x00 Access: Read/Write
31 16
R
saddr[31–16]
W
Reset All zeros
15 0
R
saddr[15–0]
W
Reset All zeros
Figure 12-15. TCD Word 0 (TCDn.saddr) Field
Table 12-16. TCD Word 0 (TCDn.saddr) Field Description
Bits Name Description
31–0 saddr Source address. Memory address pointing to the source data.