Information

DMA Controller (DMAC)
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
12-16 Freescale Semiconductor
A channel’s ability to preempt another channel can be disabled by setting the DPA bit in the DCHPRI
register. When a channel’s preempt ability is disabled, that channel cannot suspend a lower priority
channel’s data transfer; regardless of the lower priority channel’s ECP setting. This allows for a pool of
low priority, large data moving channels to be defined. These low priority channels can be configured to
not preempt each other, thus preventing a low priority channel from consuming the preempt slot normally
available a true, high priority channel.
Figure 12-14 shows the DMA clear DONE status register.
Table 12-14 defines the DCHPRI fields.
12.3.12 Transfer Control Descriptor (TCD)
Each channel requires a 32-byte transfer control descriptor for defining the desired data movement
operation. The channel descriptors are stored in the local memory in sequential order: channel 0, channel
Offset 0x100 + n Access: Read/Write
76 5 4 3 0
R
ECP DPA — CHPRI[3:0]
W
Reset 0 0 0 0 nnnn
Figure 12-14. DMA Clear DONE Status Register
Table 12-14. DCHPRIn Field Descriptions
Bits Name Description
7 ECP Enable channel preemption.
0 Channel n cannot be suspended by a higher priority channel’s service request.
1 Channel n can be temporarily suspended by the service request of a higher priority channel.
6 DPA Disable preempt ability.
0 Channel n can suspend a lower priority channel.
1 Channel n cannot suspend any channel, regardless of channel priority.
5–4 — Reserved
3–0 CHPRI Channel n arbitration priority. Channel priority when fixed-priority arbitration is enabled.