Information
DMA Controller (DMAC)
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
12-14 Freescale Semiconductor
one in any bit position clears the corresponding channel’s error status; a zero in any bit position has no
effect. DMACERR is provided so the error indicator for a single channel can easily be cleared.
See Table 12-12 for the DMAERR definition.
12.3.10 DMA General Purpose Output Register (DMAGPOR)
The DMAGPOR register, as shown in Figure 12-13, provides a general purpose register in the
programmer’s model that outputs the register contents.
Offset 0x02C Access: w1c
31 16
R
—
W
Reset All zeros
1514131211109876543210
RERR1
5
ERR
14
ERR
13
ERR
12
ERR
11
ERR
10
ERR
09
ERR
08
ERR
07
ERR
06
ERR
05
ERR
04
ERR
03
ERR
02
ERR
01
ERR
00
W w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c
Reset All zeros
Figure 12-12. DMA Error Register (DMAERR)
Table 12-12. DMAERR Field Descriptions
Bits Name Description
31–16 — Reserved
15–0 INTn DMA error n (write one to clear)
0 An error in channel n has not occurred.
1 An error in channel n has occurred.
Offset 0x038 Access: Read/Write
31 16
R
—
W
Reset All zeros
15 131211 76543210
R
—
DMA_
PRIORITY
—
SNOOP_
ENABLE
—
ERROR_
DISABLE
—
RD_SAFE_
ENABLE
—
W
Reset All zeros
Figure 12-13. DMA General Purpose Output Register (DMAGPOR)