Information

DMA Controller (DMAC)
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 12-13
interrupt controller. During the execution of the interrupt service routine associated with any given
channel, it is software’s responsibility to clear the appropriate bit, negating the interrupt request. Typically,
a write to the DMACINT register in the interrupt service routine is used for this purpose.
The state of any given channel’s interrupt request is directly affected by writes to this register; it is also
affected by writes to the DMACINT register. On writes to DMAINT, a one in any bit position clears the
corresponding channel’s interrupt request. A zero in any bit position has no affect on the corresponding
channel’s current interrupt status. The DMACINT register is provided so the interrupt request for a single
channel can easily be cleared without the need to perform a read-modify-write sequence to DMAINT.
Table 12-11 defines the DMAINT fields.
12.3.9 DMA Error Register (DMAERR)
DMAERR, shown in Figure 12-12, provides a bit map for the 16 channels, signaling the presence of an
error for each channel. The DMA engine signals the occurrence of a error condition by setting the
appropriate bit in this register. The outputs of this register are enabled by the contents of the DMAEEI
register, logically summed across the 16 channels to form the “group 0” error interrupt request, which is
then routed to the platform’s interrupt controller. During execution of the interrupt service routine
associated with any DMA errors, it is software’s responsibility to clear the appropriate bit, negating the
error interrupt request; typically, a write to the DMACERR register in the interrupt service routine is used
for this purpose. Recall that the normal DMA channel completion indicators, setting the transfer control
descriptor done flag and the possible assertion of an interrupt request, are not affected when an error is
detected.
The contents of this register can also be polled, and a non-zero value indicates the presence of a channel
error regardless of the state of the DMAEEI register. The state of any given channel’s error indicators is
affected by writes to this register; it is also affected by writes to DMACERR. On writes to DMAERR, a
Offset 0x024 Access: w1c
31 16
R
—
W
Reset All zeros
1514131211109876543210
R INT15 INT14 INT13 INT12 INT11 INT10 INT09 INT08 INT07 INT06 INT05 INT04 INT03 INT02 INT01 INT00
W w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c
Reset All zeros
Figure 12-11. DMA Interrupt Request Register Low (DMAINT)
Table 12-11. DMAINT Field Descriptions
Bits Name Description
31–16 — Reserved
15–0 INTn DMA interrupt request n (write one to clear)
0 The interrupt request for channel n is cleared.
1 The interrupt request for channel n is active.