Information

DMA Controller (DMAC)
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
12-12 Freescale Semiconductor
Table 12-9 defines DMASSRT fields.
12.3.7 DMA Clear DONE Status (DMACDNE)
DMACDNE, shown in Figure 12-10, provides a simple memory-mapped mechanism to clear the DONE
bit in the TCD of the given channel. The data value on a register write causes the DONE bit in the
corresponding transfer control descriptor to be cleared. A data value of 64 to 127 (regardless of the number
of implemented channels) provides a global clear function, forcing all DONE bits to be cleared. If bit 7 is
set, the command is ignored. This allows multiple byte registers to be written as a 32-bit word. Reads of
this register return all zeros.
Table 12-10 shows the DNACDNE fields.
12.3.8 DMA Interrupt Request Register (DMAINT)
DMAINT, shown in Figure 12-11, provide a bit map for the implemented 16 channels, signaling the
presence of an interrupt request for each channel. The DMA engine signals the occurrence of a
programmed interrupt upon completion of a data transfer as defined in the transfer control descriptor by
setting the appropriate bit in this register. The outputs of this register are directly routed to the platform’s
Table 12-9. DMASSRT Field Descriptions
Bits Name Description
7 NOP No operation.
0 Normal operation.
1 No operation, ignore bits 6–0.
6–0 SSRT Set START bit (channel service request).
0–15 Set the corresponding channel’s TCD.start.
16–63 Reserved
64–127 Set all TCD.start bits.
Offset 0x01F Access: Read/Write
76 0
R
NOP CDNE[6:0]
W
Reset All zeros
Figure 12-10. DMA Clear DONE Status Register
Table 12-10. DMACDNE Field Descriptions
Bits Name Description
7 NOP No operation
0 Normal operation.
1 No operation, ignore bits 6–0.
6–0 CDNE Clear DONE status bit.
0–15 Clear the corresponding channel’s DONE bit.
16–63 Reserved
64–127 Clear all TCD DONE bits.