Information

DMA Controller (DMAC)
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 12-11
12.3.5 DMA Clear Error (DMACERR)
DMACEER, shown in Figure 12-8, provides a simple memory-mapped mechanism to clear a given bit in
the DMAERR register to disable the error condition flag for a given channel. The given value on a register
write causes the corresponding bit in DMAERR to be cleared. A data value of 64 to 127 (regardless of the
number of implemented channels) provides a global clear function, forcing the entire contents of
DMAERR to be zeroed, clearing all channel error indicators. If bit 7 is set, the command is ignored. This
allows multiple-byte registers to be written as a 32-bit word. Reads of this register return all zeros.
Table 12-8 defines the DMACERR fields.
12.3.6 DMA Set START Bit (DMASSRT)
DMASSRT, shown in Figure 12-9, provides a simple memory-mapped mechanism to set the START bit
in the TCD of the given channel. The data value on a register write causes the START bit in the
corresponding Transfer Control Descriptor to be set. A data value of 64 to 127 (regardless of the number
of implemented channels) provides a global set function, forcing all START bits to be set. If bit 7 is set,
the command is ignored. This allows multiple byte registers to be written as a 32-bit word. Reads of this
register return all zeros.
Offset 0x01D Access: Read/Write
76 0
R
NOP CERR[6–0]
W
Reset All zeros
Figure 12-8. DMA Clear Error Register
Table 12-8. DMACERR Field Descriptions
Bits Name Description
7 NOP No operation.
0 Normal operation.
1 No operation, ignore bits 6–0.
6–0 CERR Clear error indicator.
0–15 Clear corresponding bit in DMAERR.
16–63 Reserved
64–127 Clear all bits in DMAERR.
Offset 0x01E Access: Read/Write
76 0
R
NOP SSRT[6:0]
W
Reset All zeros
Figure 12-9. DMA Set START Bit Register