Information

DMA Controller (DMAC)
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
12-10 Freescale Semiconductor
Table 12-6 defines the DMACEEI fields.
12.3.4 DMA Clear Interrupt Request (DMACINT)
DMACINT, shown in Figure 12-7, provides a simple memory-mapped mechanism to clear a given bit in
the DMAINT register to disable the interrupt request for a given channel. The given value on a register
write causes the corresponding bit in DMAINT to be cleared. A data value of 64 to 127 (regardless of the
number of implemented channels) provides a global clear function, forcing the entire contents of
DMAINT to be zeroed, disabling all DMA interrupt requests. If bit 7 is set, the command is ignored. This
allows multiple-byte registers to be written as a 32-bit word. Reads of this register return all zeros.
Table 12-7 defines the DMACINT fields.
Offset 0x01B Access: Read/Write
76 0
R
NOP CEEI[6–0]
W
Reset All zeros
Figure 12-6. DMA Clear Enable Error Interrupt Register
Table 12-6. DMACEEI Field Descriptions
Bits Name Description
7 NOP No operation.
0 Normal operation.
1 No operation, ignore bits 6–0.
6–0 CEEI Clear enable error interrupt.
0–15 Clear corresponding bit in DMAEEI.
16–63 Reserved
64–127 Clear all bits in DMAEEI.
Offset 0x01C Access: Read/Write
76 0
R
NOP CINT[6–0]
W
Reset All zeros
Figure 12-7. DMA Clear Interrupt Request Register
Table 12-7. DMACINT Field Descriptions
Bits Name Description
7 NOP No operation.
0 Normal operation.
1 No operation, ignore bits 6–0.
6–0 CINT Clear interrupt request.
0–15 Clear the corresponding bit in DMAINT.
16–63 Reserved
64–127 Clear all bits in DMAINT.