Information
DMA Controller (DMAC)
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 12-9
See Table 12-4 for the DMAEEI definition.
12.3.2 DMA Set Enable Error Interrupt (DMASEEI)
DMASEEI, shown in Figure 12-5, provides a simple memory-mapped mechanism to set a given bit in the
DMAEEI register to enable the error interrupt for a given channel. The data value on a register write causes
the corresponding bit in DMAEEI to be set. A data value of 64 to 127 (regardless of the number of
implemented channels) provides a global set function, forcing the entire contents of DMAEEI to be
asserted. If bit 7 is set, the command is ignored. This allows multiple-byte registers to be written as a 32-bit
word. Reads of this register return all zeros.
Table 12-5 defines the DMASEEI fields.
12.3.3 DMA Clear Enable Error Interrupt (DMACEEI)
The DMACEEI register, shown in Figure 12-6, provides a simple memory-mapped mechanism to clear a
given bit in the DMAEEI register to disable the error interrupt for a given channel. The data value on a
register write causes the corresponding bit in DMAEEI to be cleared. A data value of 64 to 127 (regardless
of the number of implemented channels) provides a global clear function, forcing the entire contents of
DMAEEI to be zeroed, disabling all DMA request inputs. If bit 7 is set, the command is ignored. This
allows multiple-byte registers to be written as a 32-bit word. Reads of this register return all zeros.
Table 12-4. DMAEEI Field Descriptions
Bits Name Description
31–16 — Reserved
15–0 EEIn Enable error interrupt n.
0 The error signal for channel n does not generate an error interrupt.
1 The assertion of the error signal for channel n generate an error interrupt request.
Offset 0x01A Access: Read/Write
76 0
R
NOP SEEI[6–0]
W
Reset All zeros
Figure 12-5. DMA Set Enable Error Interrupt Register
Table 12-5. DMASEEI Field Descriptions
Bits Name Description
7 NOP No operation.
0 Normal operation.
1 No operation, ignore bits 6–0.
6–0 SEEI Set enable error interrupt.
0–15 Set the corresponding bit in DMAEEI.
16–63 Reserved
64–127 Set all bits in DMAEEI.