Information

DMA Controller (DMAC)
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
12-8 Freescale Semiconductor
12.3.1 DMA Enable Error Interrupt Register (DMAEEI)
DMAEEI provides a bit map for the 16 channels to enable the error interrupt signal for each channel. The
state of any given channel’s error interrupt enable is directly affected by writes to this register; it is also
affected by writes to DMASEEI and DMACEEI. DMASEEI and DMACEEI are provided so that the error
interrupt enable for a single channel can easily be modified without the need to perform a
read-modify-write sequence to DMAEEI.
Both the DMA error indicator and this error interrupt enable flag must be asserted before an error interrupt
request for a given channel is asserted.
Figure 12-4 shows the DMA enable error interrupt register.
4 DOE Destination offset error.
0 No destination offset configuration error.
1 The last recorded error was a configuration error detected in the TCD.doff field. TCD.doff is
inconsistent with TCD.dsize.
3 NCE Nbytes/citer configuration error.
0 No nbytes/citer configuration error.
1 The last recorded error was a configuration error detected in the TCD.nbytes or TCD.citer fields.
TCD.nbytes is not a multiple of TCD.ssize and TCD.dsize, or TCD.citer is equal to zero, or
TCD.citer.e_link is not equal to TCD.biter.e_link.
2 SGE Scatter/gather configuration error.
0 No scatter/gather configuration error.
1 The last recorded error was a configuration error detected in the TCD.dlast_sga field. This field is
checked at the beginning of a scatter/gather operation after major loop completion if TCD.e_sg is
enabled. TCD.dlast_sga is not on a 32 byte boundary.
1 SBE Source bus error.
0 No source bus error.
1 The last recorded error was a bus error on a source read.
0 DBE Destination bus error.
0 No destination bus error.
1 The last recorded error was a bus error on a destination write.
Offset 0x014 Access: Read/Write
31 16
R
—
W
Reset All zeros
1514131211109876543210
R
EEI15 EEI14 EEI13 EEI12 EEI11 EEI10 EEI09 EEI08 EEI07 EEI06 EEI05 EEI04 EEI03 EEI02 EEI01 EEI00
W
Reset All zeros
Figure 12-4. DMA Enable Error Interrupt Register (DMAEEI)
Table 12-3. DMAES Field Descriptions (continued)
Bits Name Value