Information

DMA Controller (DMAC)
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 12-7
descriptor done flag and the possible assertion of an interrupt request, are not affected when an error is
detected. See Table 12-3 for the DMAES definition.
Figure 12-3 shows the DMA error status register.
Offset 0x004 Access: Read Only
31 30 17 16
R VLD
—
ECX
W
Reset All zeros
151413 876543210
R
—
CPE ERRCHN[5:0] SAE SOE DAE DOE NCE SGE SBE DBE
W
Reset All zeros
Figure 12-3. DMA Error Status Register (DMAES)
Table 12-3. DMAES Field Descriptions
Bits Name Value
31 VLD Logical OR of all the DMAERR status bits.
0 No DMAERR bits are set.
1 At least one DMAERR bit is set indicating a valid error exists that has not been cleared.
30–17 — Reserved
16 ECX Transfer cancelled.
0 No cancelled transfers
1 The last recorded entry was a cancelled transfer via the error cancel transfer input.
15 — Reserved
14 CPE Channel priority error.
0 No channel priority error.
1 The last recorded error was a configuration error in the channel priorities. All channel priorities are not
unique.
13–8 ERRCHN Error channel number or cancelled channel number. The channel number of the last recorded error
(excluding CPE errors) or last recorded transfer that was error cancelled.
7 SAE Source address error.
0 No source address configuration error.
1 The last recorded error was a configuration error detected in the TCD.saddr field. TCD.saddr is
inconsistent with TCD.ssize.
6 SOE Source offset error.
0 No source offset configuration error.
1 The last recorded error was a configuration error detected in the TCD.soff field. TCD.soff is
inconsistent with TCD.ssize.
5 DAE Destination address error.
0 No destination address configuration error.
1 The last recorded error was a configuration error detected in the TCD.daddr field. TCD.daddr is
inconsistent with TCD.dsize.