Information

DMA Controller (DMAC)
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
12-6 Freescale Semiconductor
12.3 DMA Error Status (DMAES)
The DMAES register provides information concerning the last recorded channel error. Channel errors can
be caused by a configuration error (an illegal setting in the transfer control descriptor or an illegal priority
register setting in fixed arbitration mode) or an error termination to a bus master read or write cycle.
A configuration error is caused when the starting source or destination address, source or destination
offsets, minor loop byte count and the transfer size represent an inconsistent state. The addresses and
offsets must be aligned on 0-modulo-transfer_size boundaries, and the minor loop byte count must be a
multiple of the source and destination transfer sizes. All source reads and destination writes must be
configured to the natural boundary of the programmed transfer size respectively. In fixed arbitration mode,
a configuration error is caused by any two channel priorities. All channel priority levels within the
“group 0” must be unique. If a scatter/gather operation is enabled upon channel completion, a
configuration error is reported if the scatter/gather address (dlast_sga) is not aligned on a 32 byte boundary.
If minor loop channel linking is enabled upon channel completion, a configuration error is reported when
the link is attempted if the TCD.citer.e_link bit does not equal the TCD.biter.e_link bit. All configuration
error conditions except scatter/gather and minor loop link error are reported as the channel is activated and
assert an error interrupt request, if enabled. A scatter/gather configuration error is reported when the
scatter/gather operation begins at major loop completion when properly enabled. A minor loop channel
link configuration error is reported when the link operation is serviced at minor loop completion.
If a system bus read or write is terminated with an error, the data transfer is stopped and the appropriate
bus error flag set. In this case, the state of the channel's transfer control descriptor is updated by the DMA
engine with the current source address, destination address and current iteration count at the point of the
fault. When a system bus error occurs, the channel is terminated after the read or write transaction which
is already pipelined after errant access, has completed. If a bus error occurs on the last read prior to
beginning the write sequence, the write executes using the data captured during the bus error. If a bus error
occurs on the last write prior to switching to the next read sequence, the read sequence executes before the
channel is terminated due to the destination bus error.
A transfer may be cancelled by software via the DMACR[CX] bit or hardware via the dma_cancel_xfer
input signal. When a cancel transfer request is recognized, the dma_engine stops processing the channel.
The current read-write sequence is allowed to finish. If the cancel occurs on the last read-write sequence
of a major or minor loop, the cancel request is discarded and the channel retires normally.
The error cancel transfer is the same as a cancel transfer except the DMAES register is updated with the
cancelled channel number and error cancel bit is set. The TCD of a cancelled channel has the source
address and destination address of the last transfer saved in the TCD. It is the responsibility of the user to
initialize the TCD again should the channel need to be restarted because the aforementioned fields have
been modified by the dma_engine and no longer represent the original parameters. When a transfer is
cancelled via the error cancel transfer mechanism (setting the DMACR[ECX] or asserting the
dma_err_cancel_xfer input), the channel number is loaded into the ERRCHN field and the ECX and VLD
bits are set are set in the DMAES register. In addition, an error interrupt may be generated if enabled.
SeeSection 12.3.9, “DMA Error Register (DMAERR),” for error interrupt details.
The occurrence of any type of error causes the DMA engine to immediately stop, and the appropriate
channel bit in the DMA error register to be asserted. At the same time, the details of the error condition
are loaded into the DMAES register. The major loop complete indicators, setting the transfer control