Information

DMA Controller (DMAC)
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 12-5
16 ECX Error cancel transfer.
0 Normal operation.
1 Cancel the remaining data transfer in the same fashion as the CX cancel transfer. Stop the executing
channel and force the minor loop to be finished. The cancel takes effect after the last write of the current
read/write sequence. The ECX bit clears itself after the cancel has been honored. In addition to
cancelling the transfer, the ECX treats the cancel as an error condition; thus updating the DMAES
register and generating an optional error interrupt (see Section 12.3, “DMA Error Status (DMAES)”).
15–8 — Reserved
7 EMLM Enable minor loop mapping.
0 Minor loop mapping disabled. TCDn.word2 is defined as a 32-bit nbytes field.
1 Minor loop mapping enabled. When set, TCDn.word2 is redefined to include individual enable fields,
an offset field and the nbytes field. The individual enable fields allow the minor loop offset to be applied
to the source address, the destination address, or both. The nbytes field is reduced when either offset
is enabled.
6 CLM Continuous link mode.
0 A minor loop channel link made to itself will go through channel arbitration before being activated
again.
1 A minor loop channel link made to itself will not go through channel arbitration before being activated
again. Upon minor loop completion, the channel will active again if that channel has a minor loop
channel link enabled and the link channel is itself. This effectively applies the minor loop offsets and
restarts the next minor loop.
5 HALT Halt DMA operations.
0 Normal operation.
1 Stall the start of any new channels. Executing channels are allowed to complete. Channel execution
resumes when the HALT bit is cleared.
4 HOE Halt on error.
0 Normal operation.
1 Any error causes the HALT bit to be set. Subsequently, all service requests will be ignored until the
HALT bit is cleared.
3—Reserved
2 ERCA Enable round robin channel arbitration.
0 Fixed priority arbitration is used for channel selection.
1 Round robin arbitration is used for channel selection.
1 EDBG Enable debug.
0 The assertion of the ipg_debug input is ignored.
1 The assertion of the ipg_debug input causes the DMA to stall the start of a new channel. Executing
channels are allowed to complete. Channel execution resumes when either the ipg_debug input is
negated or the EDBG bit is cleared.
0 EBW Enable buffered writes.
0 The bufferable write signal (hprot[2]) is not asserted during AHB writes.
1 The bufferable write signal (hprot[2]) is asserted on all AHB writes except for the last write sequence
write sequence.
Table 12-2. DMA Control Register (DMACR) Field Descriptions (continued)
Bits Name Description