Information

DMA Controller (DMAC)
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
12-4 Freescale Semiconductor
= 0–15”). In round robin arbitration mode, the channel priorities are ignored and the channels within this
group are cycled through without regard to priority.
Minor loop offsets are address offset values added to the final source address (saddr) or destination address
(daddr) upon minor loop completion. When minor loop offsets are enabled, the minor loop offset (mloff)
is added to the final source address (saddr), or the final destination address (daddr), or both prior to the
addresses being written back into the TCD. If the major loop is complete, the minor loop offset is ignored
and the major loop address offsets (slast and dlast_sga) are used to compute the next saddr and daddr
values.
When minor loop mapping is enabled (DMACR[EMLM] = 1), TCD word2 is redefined. A portion of TCD
word2 is used to specify multiple fields: an source enable bit (smloe) to specify the minor loop offset
should be applied to the source address (saddr) upon minor loop completion, an destination enable bit
(dmloe) to specify the minor loop offset should be applied to the destination address (daddr) upon minor
loop completion, and the sign extended minor loop offset value (mloff). The same offset value (mloff) is
used for both source and destination minor loop offsets. When either minor loop offset is enabled (smloe
set or dmloe set), the nbytes field is reduced to 8 bits. When both minor loop offsets are disabled (smloe
cleared and dmloe cleared), the nbytes field becomes a 30-bit vector.
Figure 12-2 shows the DMA control register.
Table 12-2 describes the DMACR fields.
Offset 0x000 Access: Read/Write
31 18 17 16
R
—CXECX
W
Reset All zeros
15 876543210
R
—EMLMCLM HALT HOE — ERCA EDBG EBW
W
Reset1110010000000000
Figure 12-2. DMA Control Register (DMACR)
Table 12-2. DMA Control Register (DMACR) Field Descriptions
Bits Name Description
31–18 — Reserved
17 CX Cancel transfer.
0 Normal operation.
1 Cancel the remaining data transfer. Stop the executing channel and force the minor loop to be finished.
The cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself
after the cancel has been honored. This cancel retires the channel normally as if the minor loop was
completed.