Information

DMA Controller (DMAC)
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 12-3
to a reserved memory location results in a bus error. Reserved memory locations are indicated in the
memory map. Table 12-1 is a 32-bit view of the DMA memory map.
12.2.1 DMA Control Register (DMACR)
The 32-bit DMACR defines the basic operating configuration of the DMA. There is a single group of
DMA channels labeled as, “group 0,” which contain channel numbers 0–15.
Arbitration within this group can be configured to use either a fixed priority or a round robin. In fixed
priority arbitration, the highest priority channel requesting service is selected to execute. The priorities are
assigned by the channel priority registers (see Section 12.3.11, “DMA Channel n Priority (DCHPRIn), n
Table 12-1. DMAC Register Summary
Offset Register Access Reset Section/Page
Block Base Address: 0x2_C000
0x000 DMACR—DMA Control Register R/W 0x0000_E400 12.2.1/12-3
0x004 DMAES—DMA Error Status Register R 0x0000_0000 12.3/12-6
0x008–
0x010
Reserved — — —
0x014 DMAEEI—DMA enable error interrupt register R/W 0x0000_0000 12.3.1/12-8
0x018–
0x019
Reserved — — —
0x01A DMASEEI—DMA Set Enable Error Interrupt R/W 0x0000 12.3.2/12-9
0x01B DMACEEI—DMA Clear Enable Error Interrupt R/W 0x0000 12.3.3/12-9
0x01C DMACINT—DMA Clear Interrupt Request R/W 0x0000 12.3.4/12-10
0x01D DMACERR—DMA Clear Error R/W 0x0000 12.3.5/12-11
0x01E DMASSRT—DMA Set START Bit R/W 0x0000 12.3.6/12-11
0x01F DMACDNE—DMA Clear DONE Status Bit R/W 0x0000 12.3.7/12-12
0x020 Reserved — — —
0x024 DMAINT—DMA interrupt request register w1c 0x0000_0000 12.3.8/12-12
0x028 Reserved — — —
0x02C DMAERR—DMA error register w1c 0x0000_0000 12.3.9/12-13
0x030–
0x034
Reserved — — —
0x038 DMAGPOR—DMA general purpose output register R/W 0x0000_0000 12.3.10/12-14
0x03C–
0x0FC
Reserved — — —
0x100–
0x13C
DCHPRIn—DMA Channel n Priority Register R/W 0x0000_nnnn 12.3.11/12-15
0x140–
0xFFC
Reserved — — —