Information

DMA Controller (DMAC)
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
12-2 Freescale Semiconductor
be transferred is statically known, and is not defined within the data packet itself. The DMA hardware
supports:
• 16 Channels
• 32-byte transfer control descriptor per channel stored in local memory
• 32 bytes of data registers, used as temporary storage to support burst transfers
Throughout this section, n is used to reference the channel number. Additionally, data sizes are defined as
byte (8-bit), half-word (16-bit), word (32-bit), and double word (64-bit).
12.1.1 Features
The DMA module supports the following features:
• All data movement via dual-address transfers: read from source and write to destination
— Programmable source, destination addresses, transfer size, plus support for enhanced
addressing modes
• Transfer control descriptor organized to support two-deep, nested transfer operations
— An inner data transfer loop defined by a “minor” byte transfer count
— An outer data transfer loop defined by a “major” iteration count
• Channel service request via one of two methods:
— Explicit software initiation
— Initiation via a channel-to-channel linking mechanism for continuous transfers
– Independent channel linking at end of minor loop and/or major loop
For both the methods, one service request per execution of the minor loop is required
• Support for fixed-priority and round-robin channel arbitration
• Channel completion reported via optional interrupt requests
— One interrupt per channel, optionally asserted at completion of major iteration count
— Error terminations are optionally enabled per channel, and logically summed together to form
a small number of error interrupt outputs
• Support for scatter/gather DMA processing
12.2 DMAC Memory Map/Register Definition
The DMA programming model is partitioned into two sections, both mapped into the IPIslave space: the
first region defines a number of registers providing control functions while the second region corresponds
to the local transfer control descriptor memory. Reading an unimplemented register bit or memory location
returns the value of zero. Read modified write should be used for unimplemented register bits. Any access