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MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 12-1
Chapter 12
DMA Controller (DMAC)
The direct memory access (DMA) is a second-generation platform module capable of performing complex
data transfers with minimal intervention from a host processor through 16 programmable channels. The
hardware micro-architecture includes a DMA engine, which performs source and destination address
calculations, and the actual data movement operations, along with a local memory containing the transfer
control descriptors (TCD) for the channels.
Figure 12-1 shows the DMA block diagram.
Figure 12-1. DMA Block Diagram
12.1 Overview
The DMA is a highly-programmable data transfer engine, which has been optimized to minimize the
required intervention from the host processor. It is intended for use in applications where the data size to
dma_ipi_int[n – 1:0]
Register Interface
DMA
AHB Interface
data_path controladdr_path
pmodel_charb
wdata[31:0]
addr
rdata[31:0]
SRAM Transfer Control
Descriptor
(TCD)
DMA Engine
0
j
j + 1
n – 1
64