Information

MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
liv Freescale Semiconductor
Tables
Table
Number Title
Page
Number
16-126 Shared Signals................................................................................................................... 16-123
16-127 Steps for Minimum Register Initialization........................................................................ 16-124
16-128 Custom Preamble Field Descriptions................................................................................ 16-129
16-129 Received Preamble Field Descriptions ............................................................................. 16-130
16-130 Flow Control Frame Structure .......................................................................................... 16-134
16-131 Non-Error Transmit Interrupts .......................................................................................... 16-135
16-132 Non-Error Receive Interrupts............................................................................................ 16-135
16-133 Interrupt Coalescing Timing Threshold Ranges ............................................................... 16-137
16-134 Transmission Errors .......................................................................................................... 16-138
16-135 Reception Errors ............................................................................................................... 16-138
16-136 Tx Frame Control Block Description................................................................................ 16-141
16-137 Rx Frame Control Block Descriptions.............................................................................. 16-143
16-138 Supported Stack L2 Ethernet Headers .............................................................................. 16-145
16-139 Special Filer Rules ............................................................................................................ 16-149
16-140 Receive Queue Filer Interrupt Events............................................................................... 16-149
16-141 Filer Table Example—802.1p Priority Filing ................................................................... 16-150
16-142 Filer Table Example—IP Diff-Serv Code Points Filing ................................................... 16-151
16-143 Filer Table Example—TCP and UDP Port Filing............................................................. 16-152
16-144 PTP Payload Special Fields............................................................................................... 16-159
16-145 Time-Stamp Insertion Programming Requirements ......................................................... 16-161
16-146 Tx Frame Control Block Description................................................................................ 16-163
16-147 Transmit Data Buffer Descriptor (TxBD) Field Descriptions .......................................... 16-167
16-148 Receive Buffer Descriptor Field Descriptions .................................................................. 16-170
16-149 MII Interface Mode Signal Configuration ........................................................................ 16-172
16-150 Shared MII Signals............................................................................................................ 16-173
16-151 MII Mode Register Initialization Steps............................................................................. 16-173
16-152 RGMII Interface Mode Signal Configuration................................................................... 16-175
16-153 Shared RGMII Signals...................................................................................................... 16-176
16-154 RGMII Mode Register Initialization Steps ....................................................................... 16-176
17-1 I
2
C Interface Signal Descriptions ......................................................................................... 17-3
17-2 I
2
C Interface Signals—Detailed Signal Descriptions........................................................... 17-4
17-3 I
2
C Memory Map.................................................................................................................. 17-4
17-4 I2CADR Field Descriptions.................................................................................................. 17-5
17-5 I2C FDR Field Descriptions ................................................................................................. 17-6
17-6 I2CCR Field Descriptions..................................................................................................... 17-7
17-7 I2CSR Field Descriptions ..................................................................................................... 17-8
17-8 I2CDR Field Descriptions..................................................................................................... 17-9
17-9 I2CDFSRR Field Descriptions............................................................................................ 17-10
18-1 DUART Signal Overview ..................................................................................................... 18-3
18-2 DUART Signals—Detailed Signal Descriptions .................................................................. 18-3
18-3 DUART Register Summary .................................................................................................. 18-4