Information

Enhanced Secure Digital Host Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
11-54 Freescale Semiconductor
12. Check the status bit to see if a read CRC error or any other errors occurred between sending Auto
CMD12 and receiving the response.
The number of blocks left during the data transfer is accessible by reading the content of
BLKATTR[BLKCNT]. Due to the data transfers and setting PROCTL[SABGREQ] are concurrent, along
with the delay of register read and the register setting, the actual number of blocks left may not be the same
as the value read earlier. The driver should read the value of BLKATTR[BLKCNT] after the transfer is
paused and the transfer complete interrupt is received.
It is also possible that the transfer of the last block begins when the stop-at-block-gap request is sent to the
buffer. In this case, the next block gap is the actual end of the transfer, and therefore, the request is ignored.
The driver should treat this as a non-pause transfer and a common write operation.
When the write operation is paused, the data transfer inside the host system does not stop and the transfer
remains active until the data buffer is full. Therefore, avoid using the suspend command for the SDIO card.
When such command is sent, the eSDHC assumes the system switches to another function of the SDIO
card and flushes the data buffer. The eSDHC reads the resume command as a normal command with a data
transfer, and it is the driver’s responsibility to set all the relevant registers before the transfer is resumed.
If there is only one block to send when the transfer is resumed, XFERTYP[MSBSEL, BCEN, AC12EN]
are set. However, the eSDHC automatically sends CMD12 to mark the end of multi-block transfer.
11.6.3.2 Block Read
This section discusses normal read and read with pause.
11.6.3.2.1 Normal Read
For block reads, the basic unit of a data transfer is a block whose maximum size is stored in areas defined
in corresponding card specifications. A CRC is appended to the end of each block, ensuring data transfer
integrity. CMD17, CMD18, CMD53, and so on, can initiate a block read. After completing the transfer,
the card returns to the transfer state.
For multi-block reads, data blocks are continuously transferred until a stop command is issued. If the host
uses partial blocks whose accumulated length is not block aligned and blocks misalignment is not allowed,
the card which does not support partial block length, should detect the block misalignment at the beginning
of the first misaligned block and report the error, depending on its card type.
For simplicity, the software flow described below incorporates the internal DMA, and the read operation
is a multi-block read with Auto CMD12 enabled. For the other method (CPU polling status) and different
transfer nature, the internal DMA part should be removed and the alternative steps are straightforward.
1. Check the card status and wait until the card is ready for data.
2. Set the card block length.
— MMC/SD cards — use SET_BLOCKLEN (CMD16)
— SDIO cards or the I/O portion of SD Combo cards — use IO_RW_DIRECT (CMD52) to set
IO block size bit field in CCCR register (for function 0) or FBR (for functions 1–7)
3. Set eSDHC BLKATTR[BLKSIZE] to the same as the block length set in the card in step 2.
4. Set eSDHC BLKATTR[BLKCNT] with the number of blocks to send.