Information

Enhanced Secure Digital Host Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 11-47
communicate with the card, it can enable the clock and start the operation. This can be done by clearing
the SCCR[SDHCCM] bits.
11.6 Initialization/Application Information
All communication between system and cards are controlled by the host. The host sends commands of two
types: broadcast and addressed (point-to-point) commands. Note that eSDHC supports only one SDIO
card.
Broadcast commands are intended for all cards, such as GO_IDLE_STATE, SEND_OP_COND and
ALL_SEND_CID. In broadcast mode, all cards are in the open-drain mode to avoid bus contention. For
the commands of bc and bcr categories, see Section 11.6.5, “Commands for MMC/SD/SDIO.”
After the broadcast command CMD3 is issued, the cards enter standby mode. Addressed type commands
are used from this point. In this mode, the SD_CMD/SD_DAT I/O pads turn to push-pull mode, to have
the driving capability for maximum frequency operation. For the commands of ac and adtc categories, see
Section 11.6.5, “Commands for MMC/SD/SDIO.”
11.6.1 Command Send and Response Receive Basic Operation
Assuming data type WORD is an unsigned 32-bit integer, the below flow is a guideline for sending a
command to the card(s):
send_command(cmd_index, cmd_arg, other requirements)
{
WORD wCmd; // 32-bit integer to make up the data to write into the XFERTYP register, it is
// recommended to implement in a bit-field manner
wCmd = (<cmd_index> & 0x3f) << 24; // set the first 8 bits as ‘00’+<cmd_index>
set CMDTYP, DPSEL, CICEN, CCCEN, RSTTYP, and DTDSEL according to the command index;
// XFERTYP register bits
if (internal DMA is used) wCmd |= 0x1;
if (multi-block transfer) {
set XFERTYP[MSBSEL] bit;
if (finite block number) {
set XFERTYP[BCEN] bit;
if (auto12 command is to use) set XFERTYP[AC12EN] bit;
}
}
write_reg(CMDARG, <cmd_arg>); // configure the command argument
write_reg(XFERTYP, wCmd); // set XFERTYP register as wCmd value to issue the command
}
wait_for_response(cmd_index)
{
while (IRQSTAT[CC] is not set); // wait until command complete bit is set
read IRQSTAT register and check if any error bits about command are set;
if (any error bits are set) report error;
write 1 to clear IRQSTAT[CC] and all command error bits;
}
For the sake of simplicity, the function wait_for_response is implemented here by means of polling. For
an effective and formal way, the response is usually checked after the command complete interrupt is
received. By doing this, ensure the corresponding interrupt status bits are enabled.