Information

Enhanced Secure Digital Host Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 11-45
11.5.6.1 Interrupts in 1-bit Mode
In this case, the SD_DAT[1] pin is dedicated to providing the interrupt function. An interrupt is asserted
by pulling the SD_DAT[1] low from the SDIO card, until the interrupt service is finished to clear the
interrupt.
11.5.6.2 Interrupt in 4-bit Mode
As the interrupt and data line 1 share pin 8 in four-bit mode, an interrupt is only sent by the card and
recognized by the host during a specific time. This is known as the interrupt period. The eSDHC only
samples the level on pin 8 during the interrupt period. At all other times, the host ignores the level on pin 8
and treats it as the data signal. The definition of the interrupt period is different for operations with single-
and multiple-block data transfers.
For normal single data block transmissions, the interrupt period becomes active two clock cycles after the
completion of a data packet. This interrupt period lasts until after the card receives the end bit of the next
command that has a data block transfer associated with it.
For multiple block data transfers in 4-bit mode there is only a limited period of time that the interrupt
period can be active due to the limited period of data line availability between the multiple blocks of data.
This requires a more strict definition of the interrupt period. For this case, the interrupt period is limited to
two clock cycles, which begins two clocks after the end bit of the previous data block. During this
two-clock cycle interrupt period if an interrupt is pending, the SD_DAT[1] line is held low for one clock
cycle with the last clock cycle pulling SD_DAT[1] high. On completion of the interrupt period, the card
releases the SD_DAT[1] line into the high-Z state. The eSDHC samples the SD_DAT[1] during the
interrupt period when PROCTL[IABG] is set.
for further information about the SDIO card interrupt, see SDIO Card Specification v2.0.
11.5.6.3 Card Interrupt Handling
When IRQSIGEN[CINTIEN] is cleared, the eSDHC clears the interrupt request to the host system. The
host driver should clear this bit before servicing the SDIO interrupt and should set this bit again after all
interrupt requests from the card are cleared to prevent inadvertent interrupts.
If enabled by IRQSTATEN[CINTSEN], the IRQSTAT[CINT] bit can only be cleared by resetting the
SDIO interrupt source and then writing one to this bit. Merely writing to this bit has no effect.
In 1-bit mode, the eSDHC detects the SDIO interrupt with or without SD clock (to support wakeup). In
4-bit mode, the interrupt signal is sampled during the interrupt period, so there are some sample delays
between the interrupt signal from the SDIO card and the interrupt to the host system interrupt controller.
When IRQSTAT[CINT] is set and the host driver needs to start this interrupt service,
IRQSTATEN[CINTSEN] is cleared in order to clear IRQSTAT[CINT] that is latched in the eSDHC and
to stop driving the interrupt signal to the processor’s interrupt controller. The host driver must issue a
CMD52 to clear the interrupts at the card. After completion of the card interrupt service,
IRQSTATEN[CINTSEN] is set, and the eSDHC can start sampling the interrupt signal again.
See the following illustrations:
• Figure 11-25 (a) for an illustration of the SDIO card interrupt scheme