Information

Enhanced Secure Digital Host Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
11-44 Freescale Semiconductor
Generator polynomial: G(x) = x
7
+ x
3
+ 1
M(x) = (first bit)  x
n
+ (second bit)  x
n-1
+...+ (last bit)  x
0
CRC[6:0] = Remainder [(M(x)  x
7
)  G(x)]
11.5.3.4 Data Agent
The data agent handles the transactions on the four data lines. Moreover, this module also detects the busy
state from on SD_DAT[0] line, and generates read wait state by the request from the transceiver. The CRC
polynomials for the SD_DAT are as follows:
Generator polynomial: G(x) = x
16
+ x
12
+ x
5
+ 1
M(x) = (first bit)  x
n
+ (second bit)  x
n-1
+...+ (last bit)  x
0
CRC[15:0] = Remainder [(M(x)  x
16
)  G(x)]
11.5.4 Clock & Reset Manager
This module controls all the reset signals within the eSDHC. There are four types of reset signals within
eSDHC: hardware reset, software reset for all, software reset for data, and software reset for command.
All these signals are fed into this module and stable signals are generated inside the module to reset all
other modules.
This module also gates off all the inside signals. The module monitors the activities of all other modules,
supplies the clocks for them, and when enabled, automatically gates off the corresponding clocks.
11.5.5 Clock Generator
The clock generator generates the SD_CLK by dividing the internal bus clock into two stages. Refer to
Figure 11-24 for the structure of the divider, in which the term base represents the frequency of the internal
bus clock. Refer to SYSCTL[SDCLKFS] and SYSCTL[DVS] (see Section 11.4.9, “System Control
Register (SYSCTL)”) to select the divisor values.
Figure 11-24. Two Stages of Clock Divider
The first stage is a prescaler. The frequency of clock output from this stage, DIV, can be base, base/2,
base/4, ..., or base/256.
The second stage outputs the actual clock, SD_CLK, as the driving clock for all sub-modules of SD
protocol unit, and the sync FIFOs in Figure 11-20 to synchronize with the data rate from the internal data
buffer. It can be div, div/2, div/3,..., or div/16. Thus, the highest frequency of SD_CLK generated by the
internal bus clock is base while the lowest frequency is base/4096.
11.5.6 SDIO Card Interrupt
This section discusses interrupts in 1- and 4-bit modes as well as card interrupt handling.
DIVBase
1st Divisor
by
2, 4, . . . , 256
2nd Divisor
by
1, 2, 3, . . . , 16
SD_CLK