Information

Enhanced Secure Digital Host Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 11-43
• Detects bus state on SD_DAT[0] line
• Monitors interrupt from the SDIO card
• Asserts read wait signal
• Gates off SD clock when the buffer announces danger status
• Detects write-protect state and other functions
It consists of four submodules: SD transceiver, SD clock and monitor, command agent and data agent.
11.5.3.1 SD Transceiver
In the SD protocol unit, the transceiver is the main control module. It consists of a FSM and the control
module, from which the control signals for all other three modules are generated.
11.5.3.2 SD Clock and Monitor
This module monitors the signal level on all four data lines and the command lines, directly route the level
values into the register bank for the driver to debug with.
The transceiver reports the card insertion state according to the SD_CD state, or signal level on
SD_DAT[3] line when PROCTL[D3CD] is set.
The module detects the SD_WP (write protect) line. With the information of SD_WP state, the register
bank ignores the command accompanied by write operation, when the SD_WP switch is on.
If the internal data buffer is in danger and the SD clock must be gated off to avoid buffer over/underrun,
this module asserts the gate of output SD clock to shut the clock off. When the buffer danger is eliminated
when system access of the buffer catches up, the clock gate of this module is open and the SD clock is
active again.
11.5.3.3 Command Agent
The command agent deals with the transactions on SD_CMD line. See Figure 11-23 for illustration of the
structure for the command CRC shift register.
Figure 11-23. Command CRC Shift Register
The CRC polynomials for the SD_CMD are as follows:
CLR_CRC
CRC
Bus
[6]
CRC
Bus
[5]
CRC
Bus
[4]
CRC
Bus
[3]
CRC
Bus
[2]
CRC
Bus
[1]
CRC
Bus
[0]
ZERO
CRC_IN
CRC_OUT