Information

Enhanced Secure Digital Host Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
11-40 Freescale Semiconductor
When the internal DMA is not used (XFERTYP[DMAEN] is not set when the command is sent), and more
than WML[WR_WML] number of empty word slots are available and ready for receiving new data, the
eSDHC sets the IRQSTAT[BWR]. The buffer write ready interrupt is generated if it is enabled by software.
When the internal DMA is used, the eSDHC does not inform the system before all the required number of
bytes are transferred and no error is encountered. When an error occurs during the data transfer, the eSDHC
aborts the data transfer and abandons the current block. The host driver should read the content of the
DMA system address register to obtain the start address of abandoned data block. If the current data
transfer is in multi-block mode, the eSDHC does not automatically send CMD12 even though
XFERTYP[AC12EN] is set. Therefore, in this scenario, the host driver should send CMD12 and restart
the write operation from that address. It is recommended that software reset for data is applied before the
transfer is restarted after error recovery.
The eSDHC does not start fetching the data from the host system, until the WML[WR_WML] number of
words of data can be held in the buffer. If the buffer is empty and the host system does not write data in
time, the eSDHC stops the SD_CLK to avoid a data buffer underrun situation.
11.5.1.2 Read Operation Sequence
There are two ways to read data from the buffer when transferring data from the card:
• Processor core polling IRQSTAT[BRR] (interrupt or polling)
• Internal DMA
When the internal DMA is not used (XFERTYP[DMAEN] is not set when the command is sent), and more
than WML[RD_WML] number of words are available and ready for the system to fetch data, the eSDHC
sets the IRQSTAT[BRR]. The buffer read ready interrupt is generated if it is enabled by software.
When the internal DMA is used, the eSDHC does not inform the system before all the required number of
bytes are transferred and no error is encountered. When an error occurs during the data transfer, the eSDHC
aborts the data transfer and abandons the current block. The host driver should read the content of the
DMA system address register to obtain the start address of abandoned data block. If the current data
transfer is in multi-block mode, the eSDHC does not automatically send CMD12 even though
XFERTYP[AC12EN] is set. Therefore, in this scenario, the host driver should send CMD12 and restart
the read operation from that address. It is recommended that software reset for data is applied before the
transfer is restarted after error recovery.
The eSDHC does not start data transmission until the WML[RD_WML] number of words of data are in
the buffer. If the buffer is full and the host system does not read the data in time, the eSDHC stops the
SD_CLK to avoid a data buffer overrun situation.
11.5.1.3 Data Buffer Size
To use the buffer in the most optimized way, the buffer size must be known. In the eSDHC the data buffer
can hold up to 128 32-bit words, and the read and write watermark levels are each configurable from 1–128
words. The host driver may configure the values according to the system situation and requirements.
During multi-block data transfer, the maximum block length is 4096 bytes, which can satisfy all the
requirements from MMC, SDIO, and SD cards. Any block length less than this value is also allowed. The