Information

Enhanced Secure Digital Host Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 11-39
11.5.1 Data Buffer
The eSDHC uses one configurable data buffer so that data can be transferred between the internal system
bus (register bus or CSB bus) and the SD card in an optimized manner to maximize throughput between
the two clock domains (the IP peripheral clock and the master clock). See Figure 11-20 for an illustration
of the buffer scheme.
The buffer is used as temporary storage for data being transferred between the host system and the card.
The water mark levels for read and write are both configurable and can be any value between 1 and 127
words.
Figure 11-20. eSDHC Buffer Scheme
For a host read operation, when the amount of data exceeds the RD_WML value, the eSDHC sets
PRSSTAT[BREN] and either:
• Issues a DMA request to inform the system to read the data
• Issues a DMA interrupt to inform the system to read the data
When granted CSB access permission, the internal DMA burst-reads RD_WML number of words
Conversely, for a host write operation, when the amount of buffer spaces exceeds the WR_WML value,
the eSDHC sets PRSSTAT[BWEN] and either:
• Issues a DMA request to inform the system to write data to the buffer
• Issues a DMA interrupt to inform the system to write data to the buffer
When granted CSB access permission, the internal DMA burst-writes WR_WML number of words into
the buffer
11.5.1.1 Write Operation Sequence
There are two ways to write data into the buffer when the user transfers data to the card:
• Processor core polling IRQSTAT[BWR] (interrupt or polling)
• Internal DMA
eSDHC Registers
Register
Internal
DMA
Buffer
RAM
Wrapper
Buffer Control
Interface
Status
Sync
Sync
FIFOs
TxFIFO
RxFIFO
SD Bus
Interface
eSDHC Registers
Internal
DMA
Buffer
RAM
Wrapper
Buffer Control
Status
Sync
Sync
FIFOs
TxFIFO
RxFIFO
SD Bus
Interface
Interface
eSDHC Registers
Internal
DMA
Buffer
RAM
Wrapper
Buffer Control
Status
Sync
Sync
FIFOs
TxFIFO
RxFIFO
SD Bus
Interface
Bus
Logic
CSB