Information

Enhanced Secure Digital Host Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
11-38 Freescale Semiconductor
11.4.17 Host Controller Version Register (HOSTVER)
The host controller version register, shown in Figure 11-19, contains the version for the vendor and the
host controller. All the bits are read-only.
Table 11-25 describes the HOSTVER fields.
11.4.18 DMA Control Register (DCR)
This is implemented as SDHCCR as described in Section 5.2.2.12.
11.5 Functional Description
The following sections provide a brief functional description of the major system blocks, including the
data buffer, DMA CSB interface, register bank, register bus interface, dual-port memory wrapper,
data/command controller, clock and reset manager, and clock generator.
27 FEVTAC12IE Force event Auto CMD12 index error. Forces AUTOC12ERR[AC12IE] to set.
28 FEVTAC12EBE Force event Auto CMD12 end bit error. Forces AUTOC12ERR[AC12EBE] to set.
29 FEVTAC12CE Force event Auto CMD12 CRC error. Forces AUTOC12ERR[AC12CE] to set.
30 FEVTAC12TOE Force event Auto CMD12 time out error. Forces AUTOC12ERR[AC12TOE] to set.
31 FEVTAC12NE Force event Auto CMD12 not executed. Forces AUTOC12ERR[AC12NE] to set.
Offset: 0x0FC (HOSTVER) Access: Read
0 1516 2324 31
R
—
VVN SVN
W
Reset 00000000000000000001001000000001
Figure 11-19. Host Controller Version Register (HOSTVER)
Table 11-25. HOSTVER Field Descriptions
Bit Name Description
0–15 — Reserved
16–23 VVN Vendor version number. The host driver should not use this status. The upper and the lower 4-bits
indicate the version.
0x12 Freescale eSDHC version 2.2
others Reserved
24–31 SVN Specification version number. Indicates for the host controller specification version.
0x01 SD Host Specification Version 2.0, supports the test event register.
others Reserved
Table 11-24. FEVT Field Descriptions (continued)
Bit Name Description