Information

Enhanced Secure Digital Host Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 11-37
Figure 11-18 shows the force event register.
Table 11-24 describes the FEVT fields.
Offset: 0x050 (FEVT) Access: Write
012 3 4 6 7 8 9 10 11 12 13 14 15
R0
—
0
—
0
—
00 0 0 0 0 0
W FEVT
CINT
FEVT
DMAE
FEVT
AC12E
FEVT
DEBE
FEVT
DCE
FEVT
DTOE
FEVT
CIE
FEVT
CEBE
FEVT
CCE
FEVT
CTOE
Reset All zeros
16 23 24 25 26 27 28 29 30 31
R
—
0
—
00000
W FEVTCNI
BAC12E
FEVTA
C12IE
FEVTA
C12EBE
FEVTA
C12CE
FEVTA
C12TOE
FEVTA
C12NE
Reset All zeros
Figure 11-18. Force Event Register (FEVT)
Table 11-24. FEVT Field Descriptions
Bit Name Description
0 FEVTCINT Force event card interrupt. Writing 1 to this bit generates a low-level short pulse on
the internal SD_DAT[1] line, which imitates a self-clearing interrupt from the external
card. If enabled, IRQSTAT[CINT] is set and the interrupt service routine may treat this
interrupt as a normal interrupt from the external card.
1–2 — Reserved
3 FEVTDMAE Force event DMA error. Forces IRQSTAT[DMAE] to set.
4–6 — Reserved
7 FEVTAC12E Force event Auto CMD12 error. Forces IRQSTAT[AC12E] to set.
8—Reserved
9 FEVTDEBE Force event data end bit error. Forces IRQSTAT[DEBE] to set.
10 FEVTDCE Force event data CRC error. Forces IRQSTAT[DCE] to set.
11 FEVTDTOE Force event data time out error. Forces IRQSTAT[DTOE] to set.
12 FEVTCIE Force event command index error. Forces IRQSTAT[CCE] to set.
13 FEVTCEBE Force event command end bit error. Forces IRQSTAT[CEBE] to set.
14 FEVTCCE Force event command CRC error. Forces IRQSTAT[CCE] to set.
15 FEVTCCE Force event command time out error. Forces IRQSTAT[CTOE] to set.
16–23 — Reserved
24 FEVTCNIBAC12E Force event command not executed by Auto CMD12 error. Forces
AUTOC12ERR[CNIBAC12E] to set.
25–26 — Reserved