Information

Enhanced Secure Digital Host Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
11-36 Freescale Semiconductor
11.4.15 Watermark Level Register (WML)
Figure 11-17 shows the watermark level register. Both write and read watermark levels are configurable.
The value can be any number from 1–127 words.
Table 11-23 describes the WML fields.
11.4.16 Force Event Register (FEVT)
The force event register is not a physically implemented register. Rather, it is an address to which the
IRQSTAT register can be written if the corresponding bit of IRQSTATEN is set. Therefore, this register is
a write-only register and writing zero has no effect. Writing 1 to this register sets the corresponding bit of
IRQSTAT. Reading from this register always returns zeroes.
Forcing a card interrupt generates a short pulse on the SD_DAT[1] line, and the driver may treat this
interrupt as normal. The interrupt service routine may skip polling the card-interrupt source as the interrupt
is self-cleared.
13–15 MBL Max block length. Indicates the maximum block size that the host driver can read and write to
the buffer in the eSDHC. The buffer should transfer block size without wait cycles.
000 512 bytes
001 1024 bytes
010 2048 bytes
011 4096 bytes
16–31 — Reserved
Offset: 0x044 (WML) Access: Read/Write
0 7 8 1516 2324 31
R
— WR_WML — RD_WML
W
Reset 00010000000100000001000000010000
Figure 11-17. Watermark Level Register (WML)
Table 11-23. WML Field Descriptions
Bit Name Description
0–7 — Reserved.
8–15 WR_WML Write watermark level. Number of 32-bit words of watermark level in write data transfer.
Note: The minimum value is 0x02, which represents 2 words (8 bytes).
16–23 — Reserved.
24–31 RD_WML Read watermark level. Number of 32-bit words of watermark level in read data transfer.
Table 11-22. HOSTCAPBLT Field Descriptions (continued)
Bit Name Description