Information

Enhanced Secure Digital Host Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 11-35
11.4.14 Host Controller Capabilities (HOSTCAPBLT)
The host controller capabilities provide the host driver with information specific to the eSDHC
implementation. The value in this register does not change in software reset, and any write to this register
is ignored.
Figure 11-16 shows the auto CMD12 error status register.
Table 11-22 describes the HOSTCAPBLT fields.
Offset: 0x040 (HOSTCAPBLT) Access: Read
0 678910111213 15
R
—
VS33 SRS DMAS HSS
—
MBL
W
Reset00000001111100 11
16 31
R
—
W
Reset00000000000000 00
Figure 11-16. Host Capabilities Register (HOSTCAPBLT)
Table 11-22. HOSTCAPBLT Field Descriptions
Bit Name Description
0–6 — Reserved
7 VS33 Voltage support 3.3 V. This bit depends on the host system ability.
0 3.3 V not supported
1 3.3 V supported
Note: This is always set to 1.
8 SRS Suspend/resume support. Indicates if eSDHC supports suspend/resume functionality. If this
bit is 0, suspend and resume mechanism, as well as the read wait, are not supported and the
host driver should not issue suspend or resume commands.
0 Not supported
1 Supported
9 DMAS DMA support. Indicates if eSDHC is capable of using internal DMA to transfer data between
system memory and the data buffer directly.
0 DMA not supported
1 DMA supported
10 HSS High speed support. Indicates if the eSDHC supports high speed mode and the host system
can supply the SD clock frequency from 25 to 50 MHz.
0 High speed supported
1 High speed supported
11–12 — Reserved. Set to 10.