Information

Enhanced Secure Digital Host Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 11-31
11.4.12 Interrupt Signal Enable Register (IRQSIGEN)
IRQSIGEN, shown in Figure 11-14, selects which interrupt status is indicated to the host system as the
interrupt. These status bits all share the same interrupt line. Setting any of these bits enables an interrupt
generation. The corresponding status register bit generates an interrupt when the corresponding interrupt
signal enable bit is set.
Table 11-19 describes the IRQSIGEN fields.
Offset: 0x038 (IRQSIGEN) Access: Read/Write
0 2 3 4 6 7 8 9 10 11 12 13 14 15
R
—
DMAE
IEN
—
AC12E
IEN
—
DEBE
IEN
DCE
IEN
DTOE
IEN
CIE
IEN
CEBE
IEN
CCE
IEN
CTOE
IEN
W
Reset All zeros
16 22 23 24 25 26 27 28 29 30 31
R
—
CINT
IEN
CRM
IEN
CINS
IEN
BRR
IEN
BWR
IEN
DINT
IEN
BGE
IEN
TC
IEN
CC
IEN
W
Reset All zeros
Figure 11-14. Interrupt Signal Enable Register (IRQSIGEN)
Table 11-19. IRQSIGEN Field Descriptions
Bit Name Description
0–2 — Reserved
3 DMAEIEN DMA error interrupt enable
0Masked
1 Enabled
4–6 — Reserved
7 AC12EIEN Auto CMD12 error interrupt enable
0Masked
1 Enabled
8—Reserved
9 DEBEIEN Data end bit error interrupt enable
0Masked
1 Enabled
10 DCEIEN Data CRC error interrupt enable
0Masked
1 Enabled
11 DTOEIEN Data timeout error interrupt enable
0Masked
1 Enabled