Information

Enhanced Secure Digital Host Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
11-30 Freescale Semiconductor
NOTE
The eSDHC may sample the card interrupt signal during the interrupt period
and hold its value in the flip-flop. As a result of synchronization, there is a
delay in the card interrupt (which is asserted from the card) to the time the
host system is informed.
To detect a SD_CMD line conflict, the host driver must set both CTOESEN
and CCESEN bits.
15 CTOESEN Command timeout error status enable
0Masked
1 Enabled
16–22 — Reserved
23 CINTSEN Card interrupt status enable. If this bit is cleared, the eSDHC clears the interrupt request to
the system. The card interrupt detection is stopped when this bit is cleared and restarted
when this bit is set. To prevent inadvertent interrupts, the host driver should clear this bit
before servicing the card interrupt and should set this bit again after all interrupt requests
from the card are cleared.
0Masked
1 Enabled
24 CRMSEN Card removal status enable
0Masked
1 Enabled
25 CINSEN Card insertion status enable
0Masked
1 Enabled
26 BRRSEN Buffer read ready status enable
0Masked
1 Enabled
27 BWRSEN Buffer write ready status enable
0Masked
1 Enabled
28 DINTSEN DMA interrupt status enable
0Masked
1 Enabled
29 BGESEN Block gap event status enable
0Masked
1 Enabled
30 TCSEN Transfer complete status enable
0Masked
1 Enabled
31 CCSEN Command complete status enable
0Masked
1 Enabled
Table 11-18. IRQSTATEN Field Descriptions (continued)
Bit Name Description