Information

Enhanced Secure Digital Host Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 11-29
Table 11-18 describes the IRQSTATEN fields.
Offset: 0x034 (IRQSTATEN) Access: Read/Write
0 2 3 4 6 7 8 9 10 11 12 13 14 15
R
—
DMAE
SEN
—
AC12E
SEN
—
DEBE
SEN
DCE
SEN
DTOE
SEN
CIE
SEN
CEBE
SEN
CCE
SEN
CTOE
SEN
W
Reset000 1 000 1 0 1 1 1 1 1 1 1
16 22 23 24 25 26 27 28 29 30 31
R
—
CINT
SEN
CRM
SEN
CINS
SEN
BRR
SEN
BWR
SEN
DINT
SEN
BGE
SEN
TC
SEN
CC
SEN
W
Reset000 0 000 1 0 0 1 1 1 1 1 1
Figure 11-13. Interrupt Status Enable Register (IRQSTATEN)
Table 11-18. IRQSTATEN Field Descriptions
Bit Name Description
0–2 — Reserved
3 DMAESEN DMA error status enable
0Masked
1 Enabled
4–6 — Reserved
7 AC12ESEN Auto CMD12 error status enable
0Masked
1 Enabled
8—Reserved
9 DEBESEN Data end bit error status enable
0Masked
1 Enabled
10 DCESEN Data CRC error status enable
0Masked
1 Enabled
11 DTOESEN Data timeout error status enable
0Masked
1 Enabled
12 CIESEN Command index error status enable
0Masked
1 Enabled
13 CEBESEN Command end bit error status enable
0Masked
1 Enabled
14 CCESEN Command CRC error status enable
0Masked
1 Enabled