Information

Enhanced Secure Digital Host Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
11-28 Freescale Semiconductor
Table 11-15 below shows that command timeout error has higher priority than command complete. If both
bits are set, it can be assumed that the response was not received correctly.
Table 11-16 below shows that transfer complete has higher priority than data timeout error. If both bits are
set, the data transfer can be considered complete.
The relation between command CRC error and command timeout error is shown in Table 11-17 below.
11.4.11 Interrupt Status Enable Register (IRQSTATEN)
Figure 11-13 shows the interrupt status enable register. Setting the bits of IRQSTATEN enables the
corresponding interrupt status bit to be set by the specified event. If any bit is cleared, the corresponding
IRQSTAT bit is also cleared and is never set.
Table 11-15. Relation Between Command Timeout Error and Command Complete Status
Command Complete Command Timeout Error Meaning of the Status
00 —
Don’t Care 1
Response not received within 64
SD_CLK cycles
1 0 Response received
Table 11-16. Relation Between Data Timeout Error and Transfer Complete Status
Transfer Complete Data Timeout Error Meaning of the Status
00 —
0 1 Timeout occur during transfer
1 X Data transfer complete
Table 11-17. Relation Between Command CRC Error and Command Timeout Error
Command CRC Error Command Timeout Error Meaning of the Status
00 No error
0 1 Response Timeout Error
1 0 Response CRC Error
1 1 SD_CMD line conflict