Information

Enhanced Secure Digital Host Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
11-26 Freescale Semiconductor
10 DCE Data CRC error. Occurs when detecting CRC error when transferring read data on the SD_DAT line
or when detecting the write CRC status having a value other than 0b010.
0No Error
1Error
11 DTOE Data timeout error. Occurs during one of following timeout conditions:
• Busy timeout for R1b and R5b types
• Busy timeout after write CRC status
• Read data timeout
0 No error
1 Timeout
12 CIE Command index error. Occurs if a command index error occurs in the command response.
0 No error
1 Timeout [Error]
13 CEBE Command end bit error. Occurs when the end bit of a command response is 0.
0 No error
1 End bit error generated
14 CCE Command CRC error. A command CRC error is generated in two cases:
• If a response is returned and IRQSTAT[CTOE] is cleared (indicating no timeout), this bit is set when
detecting a CRC error in the command response.
• The eSDHC detects a SD_CMD line conflict by monitoring the SD_CMD line when a command is
issued. If the eSDHC drives the SD_CMD line to 1, but detects 0 on the SD_CMD line at the next
SD_CLK edge, then the eSDHC aborts the command (stop driving SD_CMD line) and sets this bit.
The CTOE bit is also set to distinguish the SD_CMD line conflict.
0 No error
1 CRC error generated
15 CTOE Command timeout error. Occurs if no response is returned within 64 SD_CLK cycles from the end bit
of the command. Also, if eSDHC detects a SD_CMD line conflict, this bit is set along with
IRQSTAT[CCE] as shown in Table 11-26.
0 No error
1 Time out
16–22 — Reserved
23 CINT Card interrupt.
• In 1-bit mode, the eSDHC detects the card interrupt without the SD clock to support wakeup.
• In 4-bit mode, the card interrupt signal is sampled during the interrupt cycle. So, there are some
sample delays between the interrupt signal from the SD card and the interrupt to the host system.
Writing 1 clears this bit. But, if the interrupt source from the SD card is not cleared, this bit is set again.
To clear this bit, the SD card interrupt source must be cleared followed by writing 1 to this bit.
When this bit is set and the host driver needs to start the interrupt service, IRQSIGEN[CINTIEN]
should be cleared to stop driving the interrupt signal to the host system. After completing the card
interrupt service, write 1 to clear this bit, set IRQSIGEN[CINTIEN], and start sampling the interrupt
signal again.
0 No card interrupt
1 Generate card interrupt
Table 11-14. IRQSTAT Field Descriptions (continued)
Bit Name Description