Information

Enhanced Secure Digital Host Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
11-24 Freescale Semiconductor
11.4.10 Interrupt Status Register (IRQSTAT)
An interrupt is generated when one of the status bits and its corresponding interrupt enable bit are set. For
all bits, writing one to a bit clears it, while writing zero keeps the bit unchanged. More than one status can
28 CLKEN SD Card Clock Enable
0 Disable the clock
1 Enable the clock
29 PEREN Peripheral clock enable. If set, the peripheral clock is always active and no automatic gating is
applied, thus SD_CLK is active only except auto gating-off during buffer danger. If cleared, the
peripheral clock is automatically off when no transaction is on the SD bus. Clearing this bit does not
stop SD_CLK immediately. The peripheral clock will be internally gated off, if none of the following
factors are met:
• Command part is reset
• Data part is reset
• Soft reset
• Command is about to send
• Clock divisor is just updated
• Continue request is just set
• This bit is set
• Card insertion is detected
• Card removal is detected
• Card external interrupt is detected
• 80 clocks for initialization phase is ongoing
0 The peripheral clock is internally gated off
1 The peripheral clock is not automatically gated off
30 HCKEN Master clock enable. If set, master clock is always active and no automatic gating is applied. If
cleared, master clock is automatically off when no data transfer is on SD bus.
Note: Master clock is the clock to the DMA engine and to the CSB interface logic.
0) Master clock is internally gated off
1) Master clock is not automatically gated off
31 IPGEN Controller clock enable. If this bit is set, the controller clock is always active and no automatic gating
is applied. The controller clock is internally gated off, if neither the following factors is met:
• Command part is reset
• Data part is reset
• Soft reset
• Command is about to send
• Clock divisor is just updated
• Continue request is just set
• This bit is set
• Card insertion is detected
• Card removal is detected
• Card external interrupt is detected
• The controller clock is not gated off
Note: The controller clock is not auto-gated off if the peripheral clock is not gated off. So, clearing
this bit only does not take effect if SYSCTL[PEREN] is not cleared.
0 The controller clock is internally gated off
1 The controller clock is not automatically gated off
Table 11-13. SYSCTL Field Descriptions (continued)
Bit Name Description