Information

Enhanced Secure Digital Host Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 11-23
7 RSTA Software reset for all. This reset affects the entire host controller except for the card-detection circuit.
Register bits of type Read only, Read/Write, Read only: write-1-to-clear, and Read/Write Automatic
clear are cleared.
During its initialization, the host driver should set this bit to reset the eSDHC. The eSDHC should
clear this bit when capabilities registers are valid and the host driver can read them. Additional use
of this bit does not affect the value of the capabilities registers. After this bit is set, it is recommended
the host driver reset the external card and re-initialize it.
0Work
1Reset
8–11 — Reserved
12–15 DTOCV Data timeout counter value. Determines the interval by which SD_DAT line timeouts are detected.
Refer to the data timeout error Section 11.4.10, “Interrupt Status Register (IRQSTAT)”, for
information on factors that dictate timeout generation. Timeout clock frequency is generated by
dividing the base clock SD_CLK value by this value. When setting this register, prevent inadvertent
timeout events by clearing IRQSTATEN[DTOESEN].
0000 SD_CLK x 2
13
0001 SD_CLK x 2
14
...
1110 SD_CLK x 2
27
1111 Reserved
16–23 SDCLKFS SD_CLK frequency select. This field, together with DVS, selects the frequency of SD_CLK pin. This
bit holds the prescaler of the base clock frequency. Only the following settings are allowed:
0x01 Base clock divided by 2
0x02 Base clock divided by 4
0x04 Base clock divided by 8
0x08 Base clock divided by 16
0x10 Base clock divided by 32
0x20 Base clock divided by 64
0x40 Base clock divided by 128
0x80 Base clock divided by 256
Multiple bits must not be set or the behavior of this prescaler is undefined.
According to the SD Physical Specification and the SDIO Card Specification version 1.2 2.0, the
maximum SD clock frequency is 50 MHz, and should never exceed this limit. The frequency of
SD_CLK is set by the following formula:
clock frequency = (base clock) / [(SDCLKFS
2)  (DVS +1)] Eqn. 11-1
For example, if the base clock frequency is 96 MHz, and the target frequency is 25 MHz, then
choosing the prescaler value of 0x1 and divisor value of 0x1 yields 24 MHz, which is the nearest
frequency less than or equal to the target. Similarly, to approach a clock value of 400 KHz, the
prescaler value of 0x04 and divisor value of 0xE yields the exact clock value of 400 KHz.
The reset value of this bit field is 0x80. So, if the input base clock is about 96 MHz, the default SD
clock after reset is 375 KHz.
Note: The base clock frequency equals the csb_clk / SCCR[SDHCCM].
24–27 DVS Divisor. Provides a more exact divisor to generate the desired SD clock frequency. The settings are
as follows:
0x0 Divide by 1
0x1 Divide by 2
...
0xE Divide by 15
0xF Divide by 16
Table 11-13. SYSCTL Field Descriptions (continued)
Bit Name Description