Information

Enhanced Secure Digital Host Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
11-22 Freescale Semiconductor
11.4.9 System Control Register (SYSCTL)
The system control register is shown in Figure 11-11.
Table 11-13 describes the SYSCTL fields.
Offset: 0x02C (SYSCTL) Access: Mixed
0 3 4 5 6 7 8 11 12 15
R
—INITA —DTOCV
W RSTD RSTC RSTA
Reset0000000000000 0 0 0
16 23 24 27 28 29 30 31
R
SDCLKFS DVS
CLKE
N
PEREN HCKEN IPGEN
W
Reset1000000000001 0 0 0
Figure 11-11. System Control Register (SYSCTL)
Table 11-13. SYSCTL Field Descriptions
Bit Name Description
0–3 — Reserved
4 INITA Initialization active. When this bit is written ‘1’, 80 SD clocks are sent to the card. After the 80 clocks
are sent, this bit is self-cleared. This bit is very useful during the card power-up period when 74 SD
clocks are needed and clock auto-gating feature is enabled.
Writing one to this bit when it is already set has no effect. Clearing this bit at any time does not affect
it. When PRSSTAT[CIHB] or PRSSTAT[CDIHB] is set, writing a one to this bit is ignored. That is,
when the command line or data line is active, writing to this bit is not allowed.
5 RSTD Software reset for SD_DAT line. The DMA and part of the data circuit are reset. The following
registers and bits are cleared by this bit:
• DATPORT register
• Buffer is cleared and initialized; PRSSTAT register
• PRSSTAT[BREN, BWEN, RTA, WTA, DLA, CDIHB]
• PROCTL[CREQ, SABGREQ]
• IRQSTAT[BRR, BWR, DINT, BGE, TC]
0Work
1Reset
6 RSTC Software reset for SD_CMD line. Only part of the command circuit is reset. The following bits are
cleared by this bit:
• PRSSTAT[CIHB]
• IRQSTAT[CC]
0Work
1Reset