Information

Enhanced Secure Digital Host Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
11-20 Freescale Semiconductor
12 IABG Interrupt at block gap. This bit is valid only in 4-bit mode of the SDIO card and selects a sample
point in the interrupt cycle. If the SDIO card cannot signal an interrupt during a multiple block
transfer, this bit should be cleared to avoid an inadvertent interrupt. When the host driver detects
an SDIO card insertion, it should set this bit according to the CCCR of the card.
0 Disable interrupt detection during a multiple block transfer.
1 Enable interrupt detection at the block gap for a multiple block transfer.
13 RWCTL Read wait control. The read wait function is optional for SDIO cards.
If the card supports read wait, set this bit to enable the read wait protocol to stop read data using
the SD_DAT[2] line. Otherwise, the eSDHC has to stop the SD clock to hold read data, which
restricts command generation. When the host driver detects an SDIO card insertion, it should set
this bit according to the CCCR of the card.
If the card does not support read wait, this bit should never be set otherwise an SD_DAT line conflict
may occur. If this bit is cleared, a stop-at-block-gap-during-read operation is also supported, but the
eSDHC stops the SD clock to pause the reading operation.
0 Disable read-wait control, and stop SD clock at block gap when the SABGREQ bit is set
1 Enable read-wait control, and assert read wait without stopping the SD clock at block gap when
PROCTL[SABGREQ] is set
14 CREQ Continue request. Restarts a transaction which was stopped using the stop-at-block-gap request.
To cancel the request, clear SABGREQ and set this bit to restart the transfer.
The eSDHC automatically clears this bit in either of the following cases:
• For a read transaction, the PRSSTAT[DLA] bit changes from 0 to 1 as a read transaction restarts.
• For a write transaction, the PRSSTAT[WTA] bit changes from 0 to 1 as the write transaction
restarts.
Therefore, it is not necessary for the host driver to clear. If SABGREQ is set, writes to CREQ would
be ignored.
0 No effect
1Restart
15 SABGREQ Stop at block gap request. Stops executing a transaction at the next block gap for both DMA and
non-DMA transfers. Until the TC bit is set, indicating a transfer completion, the host driver should
leave this bit set. Clearing SABGREQ and CREQ does not cause the transaction to restart.
Read wait is used to stop the read transaction at the block gap. The eSDHC honors
stop-at-block-gap request for write transfers. But for read transfers it requires that the SDIO card
support read wait. Therefore, the host driver should not set this bit during read transfers unless the
SDIO card supports read wait and has set read wait control to 1. Otherwise, the eSDHC stops the
SD bus clock to pause the read operation during the block gap.
For write transfers in which the host driver writes data to the data port register, the host driver
should set this bit after all block data is written. If this bit is set, the host driver should not write data
to the DATPORT register after a block is sent. When this bit is set, the host driver should not clear
this bit before IRQSTAT[TC] is set. Otherwise, the eSDHC behavior is undefined. Confirm that
IRQSTAT[TC] is enabled.
This bit affects PRSSTAT[RTA, WTA, DLA, CIHB].
0 Transfer
1 Stop or not resume yet
16–23 — Reserved
24 CDSS Card detect signal selection. Selects the source for card detection.
If CDSS = 0 and D3CD = 0, then SD
_CD is used.
If CDSS = 0 and D3CD = 1 then DAT3 will be used for card detect
0 Card detection level is selected (for normal purpose)
1 Card detection test level is selected (for test purpose)
Table 11-12. PROCTL Field Descriptions (continued)
Bit Name Description