Information

Enhanced Secure Digital Host Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 11-19
NOTE
The host driver can issue CMD0, CMD12, CMD13 (for memory) and
CMD52 (for SDIO) when the SD_DAT lines are busy during a data transfer.
These commands can be issued when PRSSTAT[CIHB] is cleared. Other
commands should be issued when PRSSTAT[CDIHB] is cleared. Possible
changes to the SD Physical Specification may add other commands to this
list in the future.
11.4.8 Protocol Control Register (PROCTL)
The protocol control register is shown in Figure 11-10.
Table 11-12 describes the PROCTL fields.
Offset: 0x028 (PROCTL) Access: Read/Write
0 45678 1112131415
R
—
WE
CRM
WE
CINS
WE
CINT
—IABG
RW
CTL
CREQ
SABG
REQ
W
Reset0000000000000000
16 23 24 25 26 27 28 29 30 31
R
— CDSS CDTL EMODE D3CD DTW —
W
Reset0000000000100000
Figure 11-10. Protocol Control Register (PROCTL)
Table 11-12. PROCTL Field Descriptions
Bit Name Description
0–4 — Reserved
5 WECRM Wake-up event enable on SD card removal. This bit enables wakeup event via card removal
assertion in the IRQSTAT register. FN_WUS (wake-up support) in CIS does not affect this bit.
0 Disable
1 Enable
6 WECINS Wake-up event enable on SD card insertion. This bit enables wakeup event via card insertion
assertion in the IRQSTAT register. FN_WUS (wake-up support) in CIS does not affect this bit.
0 Disable
1 Enable
7 WECINT Wake-up event enable on card interrupt. This bit enables wakeup event via card interrupt assertion
in the IRQSTAT register. This bit can be set to 1 if FN_WUS (wake-up support) in CIS is set to 1.
0 Disable
1 Enable
8–11 — Reserved