Information

Enhanced Secure Digital Host Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
11-18 Freescale Semiconductor
29 DLA Data line active. Indicates whether one of the SD_DAT line on SD bus is in use.
For read transactions, this bit indicates if a read transfer is executing on the SD bus. Clearing this
bit from 1 to 0 between data blocks generates a block gap event interrupt.
This bit is set in either of the following cases:
• After the end bit of the read command
• When writing a 1 to PROCTL[CREQ] to restart a read transfer
This bit is cleared in either of the following cases:
• When the end bit of the last data block is sent from the SD bus to the eSDHC
• When beginning a read wait transfer initiated by a stop at block gap request
The eSDHC waits at the next block gap by driving read wait at the start of the interrupt cycle. If the
read-wait signal is already driven (data buffer cannot receive data), the eSDHC can wait for current
block gap by continuing to drive the read-wait signal. It is necessary to support read wait in order
to use the suspend/resume function.
For write transactions, this bit indicates that a write transfer is executing on the SD bus. Clearing
this bit from 1 to 0 generates a transfer complete interrupt.
This bit is set in any of the following cases:
• After the end bit of the write command
• When writing a 1 to PROCTL[CREQ] to continue a write transfer
This bit is cleared in any of the following cases:
• When the SD card releases write-busy of the last data block, the eSDHC also detects if output
is not busy. If the SD card does not drive the busy signal after CRC status is received, the
eSDHC should consider the card drive not busy.
• When the SD card releases write-busy prior to waiting for write transfer as a result of a stop at
block gap request
0 SD_DAT line inactive
1 SD_DAT line active
30 CDIHB Command inhibit (SD_DAT). This bit is set if the SD_DAT line is active, the read transfer active is
set, or read wait is asserted. If this bit is cleared, it indicates the eSDHC can issue the next
SD/MMC command. Commands with busy signal belong to command inhibit (SD_DAT) (e.g. R1b
and R5b type). Clearing from 1 to 0 generates a transfer complete interrupt.
Note: The SD host driver can save registers for a suspend transaction after this bit has cleared
from 1 to 0.
0 Can issue command which uses the SD_DAT line
1 Cannot issue command which uses the SD_DAT line
31 CIHB Command inhibit (SD_CMD). This bit is cleared, if the SD_CMD line is not in use and the eSDHC
can issue a SD/MMC command using the SD_CMD line.
This bit is set immediately after the XFERTYP register is written. This bit is cleared when the
command response is received. Even if the CDIHB bit is set, commands using only the SD_CMD
line can be issued if this bit is cleared. Clearing from 1 to 0 generates a command complete
interrupt.
If the eSDHC cannot issue the command because of a command conflict error (refer to command
CRC error) or because of command not issued by Auto CMD12 error, this bit remains set and
IRQSTAT[CC] is not set. Status issuing Auto CMD12 is not read from this bit.
0 Can issue command using only SD_CMD line
1 Cannot issue command
Table 11-11. PRSSTAT Field Descriptions (continued)
Bit Name Description