Information

Enhanced Secure Digital Host Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 11-17
23 WTA Write transfer active. This status indicates a write transfer is active. If this bit is 0, it means no valid
write data exists in eSDHC.
This bit is set in either of the following cases:
• After the end bit of the write command.
• When writing a 1 to PROCTL[CREQ] to restart a write transfer.
This bit is cleared in either of the following cases:
• After getting the CRC status of the last data block, as specified by the transfer count (single and
multiple)
• After getting the CRC status of any block where data transmission is about to be stopped by a
stop-at-block-gap request.
During a write transaction, a IRQSTAT[BGE] interrupt is generated when this bit is changed to 0,
as result of PROCTL[SABGREQ] being set. This status is useful for the host driver in determining
when to issue commands during write busy.
0 No valid data
1 Transferring data
24 SDOFF SD clock gated off internally. Indicates the SD clock is internally gated off because of a buffer
overrun, buffer underrun, or a read pause without read-wait assertion. This bit is for the host driver
to debug data transaction on SD bus.
This status bit resets to 0, but reflects the value of the automatic clock gating and may transition to
1 if the eSDHC is idle.
25 PEROFF The internal bus clock gated off internally. This status bit indicates the internal bus clock is internally
gated off. This bit is for the host driver to debug a transaction on SD bus.
This status bit resets to 0, but reflects the value of the automatic clock gating and may transition to
1 if the eSDHC is idle.
26 HCKOFF Master clock gated off internally. This status bit indicates master clock is internally gated off. This
bit is for the host driver to debug a data transfer.
This status bit resets to 0, but reflects the value of the automatic clock gating and may transition to
1 if the eSDHC is idle.
27 IPGOFF Controller clock gated off internally. Indicates that the controller clock is internally gated off. This bit
is for the host driver to debug. The controller clock runs at csb_clk / SCCR[ESDHCCM].
This status bit resets to 0, but reflects the value of the automatic clock gating and may transition to
1 if the eSDHC is idle.
28 SDSTB SD Clock Stable
This status bit indicates that the internal card clock is stable. This bit is for the Host Driver to poll
clock status
when changing the clock frequency. It is recommended to clear SDCLKEN bit in System Control
register to
remove glitch on the card clock when the frequency is changing.
0 clock is changing frequency and not stable
1 clock is stable
Table 11-11. PRSSTAT Field Descriptions (continued)
Bit Name Description