Information

Enhanced Secure Digital Host Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
11-16 Freescale Semiconductor
13 CDPL Card detect pin level. This bit reflects the inverse value of the SD_CD
pin for the card socket.
Debouncing is not performed on this bit. This bit may be valid, but it is not guaranteed because of
a propagation delay. Use of this bit is limited to testing since it must be debounced by software. A
software reset does not affect this bit. Write to the force event register does not affect this bit. The
reset value is affected by the external card detection pin. If this bit is not used, it should be tied to 0.
0 No card present (SD_CD
=1)
1 Card present (SD_CD
=0)
14 — Reserved
15 CINS Card inserted. Indicates if a card has been inserted. The eSDHC debounces this signal so that the
host driver does not need to wait for it to stabilize. Changing from 0 to 1 generates a card-insertion
interrupt in the interrupt status register and changing from 1 to 0 generates a card removal interrupt
in the interrupt status register. A write to the force event register does not affect this bit.
The software reset for all in the system control register does not affect this bit. A software reset does
not affect this bit.
0 Power-on-reset or no card
1 Card inserted
16–19 — Reserved
20 BREN Buffer read enable. This status is used for non-DMA read transfers. The eSDHC allows for multiple
data buffers in the internal memory. This read-only flag, when set, indicates that valid data greater
than watermark level exists in the host-side buffer.
When the buffer is read, this bit is cleared. When valid data greater than watermark level is ready
in the buffer, this bit is set and a buffer read ready interrupt is generated (if the interrupt is enabled).
0 Buffer read disable
1 Buffer read enable
21 BWEN Buffer write enable. This status is used for non-DMA write transfers. The eSDHC allows for multiple
data buffers in the internal memory. This read-only flag, when set, indicates if space is available for
greater than watermark level of write data.
When the buffer is written, this bit is cleared. When the buffer can hold data greater than the
watermark level, this bit is set and a buffer write ready interrupt is generated (if the interrupt is
enabled).
0 Buffer write disable
1 Buffer write enable
22 RTA Read transfer active. This status is used for detecting completion of a read transfer.
This bit is set for either of the following conditions:
• After the end bit of the read command
• When writing a 1 to PROCTL[CREQ] to restart a read transfer
This bit is cleared for either of the following conditions:
• When the last data block as specified by block length is transferred to the system
• When all valid data blocks have been transferred to the system and no current block transfers
are being sent as a result of PROCTL[SABGREQ] being set. A transfer complete interrupt is
generated when this bit changes to 0.
0 No valid data
1 Transferring data
Table 11-11. PRSSTAT Field Descriptions (continued)
Bit Name Description