Information

Enhanced Secure Digital Host Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 11-15
11.4.7 Present State Register (PRSSTAT)
The present state register (PRSSTAT), shown in Figure 11-9, indicates the status of the eSDHC to the host
driver.
Table 11-11 describes the PRSSTAT fields.
Offset: 0x024 (PRSSTAT) Access: Read
0 3 4 7 8 9 11 12 13 14 15
R — DLSL CLSL
—
WPSPL CDPL
—
CINS
W
Reset000011111000 0000
16 19 20 21 22 23 24 25 26 27 28 29 30 31
R
—
BREN BWEN RTA WTA
SD
OFF
PER
OFF
HCK
OFF
IPG
OFF
SDSTB DLA CDIHB CIHB
W
Reset000000001111 1000
Figure 11-9. Present State Register (PRSSTAT)
Table 11-11. PRSSTAT Field Descriptions
Bit Name Description
0–3 — Reserved
4–7 DLSL SD_DAT[3:0] line signal level. These bits are used to check the SD_DAT line level to recover from
errors, and for debugging.This is especially useful in detecting the busy signal level from
SD_DAT[0]. The reset value is affected by the external pull resistors. By default, read value of this
bit field after reset is 0111, when SD_DAT[3] is pull-down and other lines are pull-up.
8 CLSL SD_CMD line signal level. This status is used to check the SD_CMD line level to recover from
errors, and for debugging. The reset value is affected by the external pull resistor, by default, read
value of this bit after reset is 1, when the command line is pull-up.
9–11 — Reserved
12 WPSPL Write protect switch pin level. The write protect switch is supported for memory and combo cards.
This bit reflects the SD_WP pin of the card socket. A software reset does not affect this bit. The
reset value is affected by the external write protect switch. If the SD_WP pin is not used, it should
be tied to 0 so that the reset value of this bit is 0 and write is enabled.
0 Write protected (SD_WP = 1)
1 Write enabled (SD_WP = 0)
PRSSTAT Bit SD_DATn
43
52
61
70