Information

Enhanced Secure Digital Host Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 11-13
Table 11-9 describes the mapping of command responses from the SD bus to the command response
registers for each response type. In the table, R[ ] refers to a bit range within the response data as
transmitted on the SD bus.
This table shows that:
• Most responses with a length of 48 (R[47–0]) have 32 bits of the response data (R[39–8]) stored in
the CMDRSP0 register.
• Responses of type R1b (Auto CMD12 responses) have response data bits R[39–8] stored in the
CMDRSP3 register.
• Responses with length 136 (R[135–0]) have 120 bits of the response data (R[127–8]) stored in the
CMDRSP0, 1, 2, and 3 registers.
To be able to read the response status efficiently, the eSDHC only stores part of the response data in the
command response registers. This enables the host driver to efficiently read 32 bits of response data in one
read cycle on a 32-bit bus system. Parts of the response, the index field, and the CRC are checked by the
eSDHC (as specified by XFERTYP[CICEN, CCCEN]) and generate an error interrupt if any error is
detected. The bit range for the CRC check depends on the response length. If the response length is 48, the
eSDHC checks R[47–1], and if the response length is 136, the eSDHC checks R[119–1].
Since the eSDHC may have a multiple block data transfer executing concurrently with a CMD_wo_DAT
command, the eSDHC stores the Auto CMD12 response in the CMDRSP3 register and the
CMD_wo_DAT response is stored in CMDRSP0. This allows the eSDHC to avoid overwriting the Auto
CMD12 response with the CMD_wo_DAT and vice versa. When the eSDHC modifies part of the
command response registers it preserves the unmodified bits.
Table 11-9. Response Bit Definition for Each Response Type
Response Type Meaning of Response
Response
Field
Response Register
R1,R1b (normal response) Card status R[39–8] CMDRSP0
R1b (Auto CMD12 response) Card status for Auto CMD12 R[39–8] CMDRSP3
R2 (CID, CSD register) CID/CSD register [127–8] R[127–8] {CMDRSP3[23:0], CMDRSP2,
CMDRSP1, CMDRSP0}
R3 (OCR register) OCR register for memory R[39–8] CMDRSP0
R4 (OCR register) OCR register for I/O R[39–8] CMDRSP0
R5, R5b SDIO response R[39–8] CMDRSP0
R6 (publish RCA) New published RCA[31–16]
and card status[15–0]
R[39–8] CMDRSP0