Information

Enhanced Secure Digital Host Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
11-12 Freescale Semiconductor
Table 11-8 shows how the response type can be determined by the command index check enable,
command CRC check enable, and response type bits.
NOTE
•In the SDIO Specification, response type notation of R5b is not defined.
R5 includes R5b in the SDIO Specification. But R5b is defined to
specify the eSDHC checks busy status after receiving a response. For
example, usually CMD52 is used as R5 but the I/O abort command
should be used as R5b.
• The CRC field for R3 and R4 is expected to be all 1s. The CRC check
should be disabled for these response types.
11.4.5 Command Response 0–3 (CMDRSP0–3)
The command response registers, shown in Figure 11-7, store the four parts of the response bits from the
card.
Table 11-8. Relation Between Parameters and Name of Response Type
Response Type
XFERTYP[RSPTYP]
Index Check Enable
XFERTYP[CICEN]
CRC Check Enable
XFERTYP[CCCEN]
Response Type
00 0 0 No Response
01 0 1 R2
10 0 0 R3, R4
10 1 1 R1, R5, R6
11 1 1 R1b, R5b
Offset: 0x010 (CMDRSP0)
0x014 (CMDRSP1)
0x018 (CMDRSP2)
0x01C (CMDRSP3)
Access: Read
0 31
RCMDRSP
W
Reset All zeros
Figure 11-7. Command Response 0–3 Register (CMDRSPn)