Information

Enhanced Secure Digital Host Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 11-11
Table 11-7 shows how register settings determine types of data transfers.
14–15 RSPTYP Response type select.
00 No response
01 Response length 136
10 Response length 48
11 Response length 48 check busy after response
16–25 — Reserved
26 MSBSEL Multi/single block select. Enables multiple block SD_DAT line data transfers. For any other
commands, this bit should be cleared. If this bit is cleared, it is not necessary to set the block
count register. (Refer to Tabl e 11 -7.)
0 Single block
1 Multiple blocks
27 DTDSEL Data transfer direction select. Defines the direction of SD_DAT line data transfers. The bit is set
by the host driver to transfer data from the SD card to the eSDHC and it is cleared for all other
commands.
0 Write (host to card)
1 Read (card to host)
28 — Reserved
29 AC12EN Auto CMD12 enable. Multiple block transfers for memory require CMD12 to stop the transaction.
If this bit is set, the eSDHC issues CMD12 automatically when the last block transfer is
completed. The host driver should not set this bit to issue commands that do not require CMD12
to stop a multiple block data transfer. In particular, secure commands defined in the Part 3 File
Security specification do not require CMD12. In a single block transfer, the eSDHC ignores this
bit.
0 Disable
1 Enable
30 BCEN Block count enable. Enables the block attributes register, which is only relevant for multiple block
transfers. When this bit is cleared, the block attributes register is disabled, which is useful in
executing an infinite transfer.
0 Disable
1 Enable
31 DMAEN DMA enable. Enables DMA functionality as described in Section 11.5.2, “DMA CSB Interface.”
If this bit is set, a DMA operation should begin when the host driver writes to the CMDINX field
of the transfer type register.
0 Disable
1 Enable
Table 11-7. Determination of Transfer Type
Multi/Single Block Select
XFERTYP[MSBSEL]
Block Count Enable
XFERTYP[BCEN]
Block Count
BLKATTR[BLKCNT]
Function
0 Don’t Care Don’t Care Single Transfer
1 0 Don’t Care Infinite Transfer
1 1 Positive Number Multiple Transfer
1 1 Zero No Data Transfer
Table 11-6. XFERTYP Field Descriptions (continued)
Bit Name Description