Information

Enhanced Secure Digital Host Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 11-9
Table 11-5 describes the CMDARG fields.
11.4.4 Transfer Type Register (XFERTYP)
The transfer type register, shown in Figure 11-6, controls the operation of data transfers. The host driver
should set this register before issuing a command followed by a data transfer, or before issuing a resume
command. To prevent data loss, the eSDHC prevents a write to the bits that are involved in the data transfer
of this register while the data transfer is active.
The host driver should check PRSSTAT[CDIHB] and PRSSTAT[CIHB] before writing to this register.
• If PRSSTAT[CDIHB] is set, any attempt to send a command with data by writing to this register is
ignored.
• If PRSSTAT[CIHB] is set, any write to this register is ignored.
Table 11-6 describes the XFERTYP fields.
Table 11-5. CMDARG Field Descriptions
Bit Name Description
0–31 CMDARG Command argument. The SD/MMC command argument is specified as bits 39–8 of the command
format in the SD or MMC Specification. If PRSSTAT[CMD] is set, this register is write-protected.
Offset: 0x00C (XFERTYP) Access: Read/Write
0 1 2 7 8 9 10 11 12 13 14 15 16 25 26 27 28 29 30 31
R
—CMDINX
CMD
TYP
DP
SEL
CICEN CCCEN —
RSP
TYP
—
MSB
SEL
DTD
SEL
—
AC12
EN
BCEN
DMA
EN
W
Reset All zeros
Figure 11-6. Transfer Type Register (XFERTYP)
Table 11-6. XFERTYP Field Descriptions
Bit Name Description
0–1 — Reserved
2–7 CMDINX Command index. These bits should be set to the command number (CMD0–63, ACMD0–63)
that is specified in bits 45–40 of the command format in the SD Memory Card Physical Layer
Specification and SDIO Card Specification.