Information

Enhanced Secure Digital Host Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
11-8 Freescale Semiconductor
Table 11-4 describes the BLKATTR fields.
11.4.3 Command Argument Register (CMDARG)
The command argument register, shown in Figure 11-5, contains the SD/MMC command argument.
Table 11-4. BLKATTR Field Descriptions
Bit Name Description
0–15 BLKCNT Block count for current transfer. This field is enabled when XFERTYP[BCEN] is set and is valid only for
multiple block transfers. The host driver should set this field to a value between 1 and the maximum block
count. The eSDHC decrements the block count after each block transfer and stops when the count
reaches zero. Clearing this field results in no data blocks being transferred.
When saving transfer context as a result of a suspend command, this field indicates the number of
blocks yet to be transferred. When restoring transfer context prior to issuing a resume command, the
host driver should write the previously saved block count.
0000 Stop count
0001 1 block
0002 2 blocks
...
FFFF 65,535 blocks
16–18 — Reserved
19–31 BLKSIZE Transfer block size. Specifies the block size for block data transfers. Values can range from one byte up
to the maximum buffer size.
The DMA always writes at least four bytes to memory. Thus, software should allocate a buffer space
rounded up to a 4-byte alighted size in order to avoid data corruption.
0000 No data transfer
0001 1 byte
0002 2 bytes
0003 3 bytes
0004 4 bytes
...
01FF 511 bytes
0200 512 bytes
...
0800 2048 bytes
1000 4096 bytes
Offset: 0x008 (CMDARG) Access: Read/Write
0 31
R
CMDARG
W
Reset All zeros
Figure 11-5. Command Argument Register (CMDARG)