Information

Enhanced Secure Digital Host Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 11-7
11.4.1 DMA System Address Register (DSADDR)
The DMA system address register contains the system memory address used for DMA transfers. Only
access this register when no transactions are executing (after transactions have stopped). The host driver
should wait until PRSSTAT[DLA] is cleared.
Figure 11-3 shows the DMA system address register.
Table 11-3 describes the DSADDR fields.
11.4.2 Block Attributes Register (BLKATTR)
The block attributes register configures the number of data blocks and the number of bytes in each block.
Only access this register when no transactions are executing (after transactions have stopped). The host
driver should wait until PRSSTAT[DLA] is cleared. During a data transfer, the following may occur:
• Reading this register may return an invalid value.
• Writing this register is ignored.
Figure 11-4 shows the DMA system address register.
Offset: 0x000 Access: Read/Write
0 31
R
DS_ADDR
W
Reset00000000000000000000000000000000
Figure 11-3. DMA System Address Register (DSADDR)
Table 11-3. DSADDR Field Descriptions
Bit Name Description
0–31 DS_ADDR DMA system address. When the eSDHC stops a DMA transfer, this register points to the system
address of the next contiguous data position.
Note: The DS_ADDR must be aligned to a four-byte boundary; the two least-significant bits must
be cleared.
Offset: 0x004 (BLKATTR) Access: Read/Write
0 1516 1819 31
R
BLKCNT — BLKSZE
W
Reset 00000000000000010000000000000000
Figure 11-4. Block Attributes Register (BLKATTR)